rockchip: enable debug uart

[u-boot] / arch / arm / mach-zynq / slcr.c

diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 05f4099aaee81712eb21d130aa0044f6fa2e37d2..2a207ae46c18c918ca874d9e69d0a850c4de81ba 100644 (file)
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -9,11 +9,13 @@
 #include <malloc.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/clk.h>
 
 #define SLCR_LOCK_MAGIC                0x767B
 #define SLCR_UNLOCK_MAGIC      0xDF0D
 
+#define SLCR_NAND_L2_SEL               0x10
+#define SLCR_NAND_L2_SEL_MASK          0x1F
+
 #define SLCR_USB_L1_SEL                        0x04
 
 #define SLCR_IDCODE_MASK       0x1F000
@@ -36,6 +38,14 @@ struct zynq_slcr_mio_get_status {
        u32 check_val;
 };
 
+static const int nand8_pins[] = {
+       0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
+};
+
+static const int nand16_pins[] = {
+       16, 17, 18, 19, 20, 21, 22, 23
+};
+
 static const int usb0_pins[] = {
        28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
 };
@@ -45,6 +55,20 @@ static const int usb1_pins[] = {
 };
 
 static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+       {
+               "nand8",
+               nand8_pins,
+               ARRAY_SIZE(nand8_pins),
+               SLCR_NAND_L2_SEL_MASK,
+               SLCR_NAND_L2_SEL,
+       },
+       {
+               "nand16",
+               nand16_pins,
+               ARRAY_SIZE(nand16_pins),
+               SLCR_NAND_L2_SEL_MASK,
+               SLCR_NAND_L2_SEL,
+       },
        {
                "usb0",
                usb0_pins,
@@ -99,34 +123,6 @@ void zynq_slcr_cpu_reset(void)
        writel(1, &slcr_base->pss_rst_ctrl);
 }
 
-/* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
-{
-       int ret;
-
-       zynq_slcr_unlock();
-
-       if (gem_id > 1) {
-               printf("Non existing GEM id %d\n", gem_id);
-               goto out;
-       }
-
-       ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
-       if (ret)
-               goto out;
-
-       if (gem_id) {
-               /* Configure GEM_RCLK_CTRL */
-               writel(1, &slcr_base->gem1_rclk_ctrl);
-       } else {
-               /* Configure GEM_RCLK_CTRL */
-               writel(1, &slcr_base->gem0_rclk_ctrl);
-       }
-       udelay(100000);
-out:
-       zynq_slcr_lock();
-}
-
 void zynq_slcr_devcfg_disable(void)
 {
        u32 reg_val;