Merge branch 'master' of git://git.denx.de/u-boot-mips

[u-boot] / arch / i386 / cpu / cpu.c

diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c
index 3010519e7461347e73d5e399992e4b5b15e813c8..2339cd41bbe71d037bc7900dd1222b83b8194528 100644 (file)
--- a/arch/i386/cpu/cpu.c
+++ b/arch/i386/cpu/cpu.c
@@ -35,28 +35,94 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
 #include <asm/interrupt.h>
 
-int cpu_init_f(void)
+/* Constructor for a conventional segment GDT (or LDT) entry */
+/* This is a macro so it can be used in initializers */
+#define GDT_ENTRY(flags, base, limit)                  \
+       ((((base)  & 0xff000000ULL) << (56-24)) |       \
+        (((flags) & 0x0000f0ffULL) << 40) |            \
+        (((limit) & 0x000f0000ULL) << (48-16)) |       \
+        (((base)  & 0x00ffffffULL) << 16) |            \
+        (((limit) & 0x0000ffffULL)))
+
+/*
+ * Set up the GDT
+ */
+
+struct gdt_ptr {
+       u16 len;
+       u32 ptr;
+} __attribute__((packed));
+
+static void reload_gdt(void)
 {
+       /* There are machines which are known to not boot with the GDT
+          being 8-byte unaligned.  Intel recommends 16 byte alignment. */
+       static const u64 boot_gdt[] __attribute__((aligned(16))) = {
+               /* CS: code, read/execute, 4 GB, base 0 */
+               [GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
+               /* DS: data, read/write, 4 GB, base 0 */
+               [GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
+               /* 16-bit CS: code, read/execute, 64 kB, base 0 */
+               [GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff),
+               /* 16-bit DS: data, read/write, 64 kB, base 0 */
+               [GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff),
+       };
+       static struct gdt_ptr gdt;
+
+       gdt.len = sizeof(boot_gdt)-1;
+       gdt.ptr = (u32)&boot_gdt;
+
+       asm volatile("lgdtl %0\n" \
+                    "movl $((2+1)*8), %%ecx\n" \
+                    "movl %%ecx, %%ds\n" \
+                    "movl %%ecx, %%es\n" \
+                    "movl %%ecx, %%fs\n" \
+                    "movl %%ecx, %%gs\n" \
+                    "movl %%ecx, %%ss" \
+                    : : "m" (gdt) : "ecx");
+}
+
+
+int x86_cpu_init_f(void)
+{
+       const u32 em_rst = ~X86_CR0_EM;
+       const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
+
        /* initialize FPU, reset EM, set MP and NE */
        asm ("fninit\n" \
-            "movl %cr0, %eax\n" \
-            "andl $~0x4, %eax\n" \
-            "orl  $0x22, %eax\n" \
-            "movl %eax, %cr0\n" );
+            "movl %%cr0, %%eax\n" \
+            "andl %0, %%eax\n" \
+            "orl  %1, %%eax\n" \
+            "movl %%eax, %%cr0\n" \
+            : : "i" (em_rst), "i" (mp_ne_set) : "eax");
 
        return 0;
 }
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
 
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
 {
+       const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+       /* turn on the cache and disable write through */
+       asm("movl       %%cr0, %%eax\n"
+           "andl       %0, %%eax\n"
+           "movl       %%eax, %%cr0\n"
+           "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
+       reload_gdt();
+
        /* Initialize core interrupt and exception functionality of CPU */
        cpu_init_interrupts ();
        return 0;
 }
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        printf ("resetting ...\n");
        udelay(50000);                          /* wait 50 ms */