}
-int cpu_init_f(void)
+int x86_cpu_init_f(void)
{
const u32 em_rst = ~X86_CR0_EM;
const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
return 0;
}
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
{
+ const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+ /* turn on the cache and disable write through */
+ asm("movl %%cr0, %%eax\n"
+ "andl %0, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
reload_gdt();
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts ();
return 0;
}
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{