mx7dsabresd: Fix LCD_PWR_EN output setting

[u-boot] / arch / m68k / cpu / mcf52x2 / interrupts.c

diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index dff8c6aa8820a000c6e8bcfe9307aa57494133b7..8cc07f2c67145f2bb611e7d34cdb57a6692e33ea 100644 (file)
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -2,46 +2,32 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #ifdef CONFIG_M5272
 int interrupt_init(void)
 {
-       volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+       intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
 
        /* disable all external interrupts */
-       intp->int_icr1 = 0x88888888;
-       intp->int_icr2 = 0x88888888;
-       intp->int_icr3 = 0x88888888;
-       intp->int_icr4 = 0x88888888;
-       intp->int_pitr = 0x00000000;
+       out_be32(&intp->int_icr1, 0x88888888);
+       out_be32(&intp->int_icr2, 0x88888888);
+       out_be32(&intp->int_icr3, 0x88888888);
+       out_be32(&intp->int_icr4, 0x88888888);
+       out_be32(&intp->int_pitr, 0x00000000);
+
        /* initialize vector register */
-       intp->int_pivr = 0x40;
+       out_8(&intp->int_pivr, 0x40);
 
        enable_interrupts();
 
@@ -51,10 +37,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-       volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+       intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
 
-       intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
-       intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
+       clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
+       setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
 }
 #endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5272 */
@@ -63,14 +49,14 @@ void dtimer_intr_setup(void)
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
        /* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
-       intp->imrl0 = 0xFFFFFFFF;
-       intp->imrh0 = 0xFFFFFFFF;
+       out_be32(&intp->imrl0, 0xffffffff);
+       out_be32(&intp->imrh0, 0xffffffff);
 #else
-       intp->imrl0 |= 0x1;
+       setbits_be32(&intp->imrl0, 0x1);
 #endif
 
        enable_interrupts();
@@ -80,11 +66,11 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-       intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-       intp->imrl0 &= 0xFFFFFFFE;
-       intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+       out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+       clrbits_be32(&intp->imrl0, 0x00000001);
+       clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */