default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
-config USE_PRIVATE_LIBGCC
- default y
-
choice
prompt "Target select"
+ optional
config TARGET_QEMU_MIPS
bool "Support qemu-mips"
config TARGET_MALTA
bool "Support malta"
+ select DYNAMIC_IO_PORT_BASE
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SWAP_IO_SPACE
+ select MIPS_L1_CACHE_SHIFT_6
config TARGET_VCT
bool "Support vct"
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
config TARGET_DBAU1X00
bool "Support dbau1x00"
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select MIPS_TUNE_4KC
config TARGET_PB1X00
bool "Support pb1x00"
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select MIPS_TUNE_4KC
+config MACH_PIC32
+ bool "Support Microchip PIC32"
+ select OF_CONTROL
+ select DM
endchoice
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
if MIPS
address and size will be prepared as zero-terminated key/value list.
The address of the enviroment is stored in register $a2.
+config MIPS_BOOT_FDT
+ bool "Hand over a flattened device tree to Linux kernel"
+ default n
+ help
+ Enable this option if you want U-Boot to hand over a flattened
+ device tree to the kernel. According to UHI register $a0 will be set
+ to -2 and the FDT address is stored in $a1.
+
endmenu
config SUPPORTS_BIG_ENDIAN
config SUPPORTS_CPU_MIPS64_R2
bool
+config CPU_MIPS32
+ bool
+ default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
+
+config CPU_MIPS64
+ bool
+ default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
+config MIPS_TUNE_4KC
+ bool
+
+config MIPS_TUNE_14KC
+ bool
+
+config MIPS_TUNE_24KC
+ bool
+
config 32BIT
bool
config 64BIT
bool
+config SWAP_IO_SPACE
+ bool
+
+config SYS_MIPS_CACHE_INIT_RAM_LOAD
+ bool
+
+config MIPS_L1_CACHE_SHIFT_4
+ bool
+
+config MIPS_L1_CACHE_SHIFT_5
+ bool
+
+config MIPS_L1_CACHE_SHIFT_6
+ bool
+
+config MIPS_L1_CACHE_SHIFT_7
+ bool
+
+config MIPS_L1_CACHE_SHIFT
+ int
+ default "7" if MIPS_L1_CACHE_SHIFT_7
+ default "6" if MIPS_L1_CACHE_SHIFT_6
+ default "5" if MIPS_L1_CACHE_SHIFT_5
+ default "4" if MIPS_L1_CACHE_SHIFT_4
+ default "5"
+
+config DYNAMIC_IO_PORT_BASE
+ bool
+
endif
endmenu