MIPS: mips64: fix typos in copyright text of start.S

[u-boot] / arch / mips / cpu / mips32 / cpu.c

diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 3ae397c8eff4160f6d37102016fbf7e634b591b1..28d5c456832be0ecbe547efb70b7ee77c243fa12 100644 (file)
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2003
  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -56,9 +40,13 @@ void flush_cache(ulong start_addr, ulong size)
        unsigned long addr = start_addr & ~(lsize - 1);
        unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
+       /* aend will be miscalculated when size is zero, so we return here */
+       if (size == 0)
+               return;
+
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -72,7 +60,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -86,7 +74,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Invalidate_D, addr);
+               cache_op(HIT_INVALIDATE_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;