Merge 'u-boot-atmel/master' into 'u-boot-arm/master'

[u-boot] / arch / mips / cpu / mips32 / cpu.c

diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 3ae397c8eff4160f6d37102016fbf7e634b591b1..50bb248bd0102ab12f04952572ecc32edc6d76b4 100644 (file)
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -56,9 +56,13 @@ void flush_cache(ulong start_addr, ulong size)
        unsigned long addr = start_addr & ~(lsize - 1);
        unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
+       /* aend will be miscalculated when size is zero, so we return here */
+       if (size == 0)
+               return;
+
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -72,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -86,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Invalidate_D, addr);
+               cache_op(HIT_INVALIDATE_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;