MIPS: start.S: simplify relocation offset calculation

[u-boot] / arch / mips / cpu / mips32 / start.S

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 9c1b2f76d09bcff61c4d617da0795b7f35b9085c..d67dafacd463a41a469310e5ce663b80cbce1ef2 100644 (file)
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -258,8 +258,7 @@ reset:
 #endif
 
        /* Set up temporary stack */
-       li      t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-       la      sp, 0(t0)
+       li      sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
        la      t9, board_init_f
        jr      t9
@@ -280,21 +279,17 @@ reset:
 relocate_code:
        move    sp, a0                  # set new stack pointer
 
+       move    s0, a1                  # save gd in s0
+       move    s2, a2                  # save destination address in s2
+
        li      t0, CONFIG_SYS_MONITOR_BASE
+       sub     s1, s2, t0              # s1 <-- relocation offset
+
        la      t3, in_ram
        lw      t2, -12(t3)             # t2 <-- uboot_end_data
        move    t1, a2
-       move    s2, a2                  # s2 <-- destination address
 
-       /*
-        * Fix $gp:
-        *
-        * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-        */
-       move    t6, gp
-       sub     gp, CONFIG_SYS_MONITOR_BASE
-       add     gp, a2                  # gp now adjusted
-       sub     s1, gp, t6              # s1 <-- relocation offset
+       add     gp, s1                  # adjust gp
 
        /*
         * t0 = source address
@@ -305,7 +300,6 @@ relocate_code:
        /*
         * Save destination address and size for later usage in flush_cache()
         */
-       move    s0, a1                  # save gd in s0
        move    a0, t1                  # a0 <-- destination addr
        sub     a1, t2, t0              # a1 <-- size
 
@@ -313,7 +307,7 @@ relocate_code:
        lw      t3, 0(t0)
        sw      t3, 0(t1)
        addu    t0, 4
-       ble     t0, t2, 1b
+       blt     t0, t2, 1b
         addu   t1, 4
 
        /* If caches were enabled, we would have to flush them here. */
@@ -380,6 +374,8 @@ in_ram:
        /* Exception handlers */
 romReserved:
        b       romReserved
+        nop
 
 romExcHandle:
        b       romExcHandle
+        nop