MIPS: unify cache initialization code

[u-boot] / arch / mips / cpu / mips64 / cpu.c

diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
index 9f45cfca5d2a983eec93f2d83ab408d7367bc2c9..1d32705b74d0cdc680c5cb8ef91f077872422b09 100644 (file)
--- a/arch/mips/cpu/mips64/cpu.c
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -9,19 +9,8 @@
 #include <command.h>
 #include <netdev.h>
 #include <asm/mipsregs.h>
-#include <asm/cacheops.h>
 #include <asm/reboot.h>
 
-#define cache_op(op, addr)                                             \
-       __asm__ __volatile__(                                           \
-       "       .set    push\n"                                         \
-       "       .set    noreorder\n"                                    \
-       "       .set    mips64\n"                                       \
-       "       cache   %0, %1\n"                                       \
-       "       .set    pop\n"                                          \
-       :                                                               \
-       : "i" (op), "R" (*(unsigned char *)(addr)))
-
 void __attribute__((weak)) _machine_restart(void)
 {
        fprintf(stderr, "*** reset failed ***\n");
@@ -37,53 +26,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        return 0;
 }
 
-void flush_cache(ulong start_addr, ulong size)
-{
-       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
-
-       /* aend will be miscalculated when size is zero, so we return here */
-       if (size == 0)
-               return;
-
-       while (1) {
-               cache_op(HIT_WRITEBACK_INV_D, addr);
-               cache_op(HIT_INVALIDATE_I, addr);
-               if (addr == aend)
-                       break;
-               addr += lsize;
-       }
-}
-
-void flush_dcache_range(ulong start_addr, ulong stop)
-{
-       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-       while (1) {
-               cache_op(HIT_WRITEBACK_INV_D, addr);
-               if (addr == aend)
-                       break;
-               addr += lsize;
-       }
-}
-
-void invalidate_dcache_range(ulong start_addr, ulong stop)
-{
-       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-       while (1) {
-               cache_op(HIT_INVALIDATE_D, addr);
-               if (addr == aend)
-                       break;
-               addr += lsize;
-       }
-}
-
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
 {
        write_c0_entrylo0(low0);