mips: Let cache.h be included from assembly source

[u-boot] / arch / mips / include / asm / cache.h

diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 5406d5d46a3bb91ccf4072477d817e812b48f5b1..83165d5c9705fcc2f41eb501eb363b15e556aba3 100644 (file)
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -1,36 +1,33 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __MIPS_CACHE_H__
 #define __MIPS_CACHE_H__
 
+#define L1_CACHE_SHIFT         CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN      (L1_CACHE_BYTES)
+
 /*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
+#ifndef __ASSEMBLY__
+/**
+ * mips_cache_probe() - Probe the properties of the caches
+ *
+ * Call this to probe the properties such as line sizes of the caches
+ * present in the system, if any. This must be done before cache maintenance
+ * functions such as flush_cache may be called.
  */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN      128
+void mips_cache_probe(void);
 #endif
 
 #endif /* __MIPS_CACHE_H__ */