+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 1994, 1995 Waldorf GmbH
* Copyright (C) 1994 - 2000, 06 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
* Author: Maciej W. Rozycki <macro@mips.com>
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_IO_H
#define _ASM_IO_H
+#include <linux/bug.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <mangle-port.h>
#include <spaces.h>
-/*
- * Slowdown I/O port space accesses for antique hardware.
- */
-#undef CONF_SLOWDOWN_IO
-
/*
* Raw operations are never swapped in software. OTOH values that raw
* operations are working on may or may not have been swapped by the bus
#define IO_SPACE_LIMIT 0xffff
-/*
- * On MIPS I/O ports are memory mapped, so we access them using normal
- * load/store instructions. mips_io_port_base is the virtual address to
- * which all ports are being mapped. For sake of efficiency some code
- * assumes that this is an address that can be loaded with a single lui
- * instruction, so the lower 16 bits must be zero. Should be true on
- * on any sane architecture; generic code does not use this assumption.
- */
-extern const unsigned long mips_io_port_base;
+#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
+
+static inline ulong mips_io_port_base(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ return gd->arch.io_port_base;
+}
-/*
- * Gcc will generate code to load the value of mips_io_port_base after each
- * function call which may be fairly wasteful in some cases. So we don't
- * play quite by the book. We tell gcc mips_io_port_base is a long variable
- * which solves the code generation issue. Now we need to violate the
- * aliasing rules a little to make initialization possible and finally we
- * will need the barrier() to fight side effects of the aliasing chat.
- * This trickery will eventually collapse under gcc's optimizer. Oh well.
- */
static inline void set_io_port_base(unsigned long base)
{
- * (unsigned long *) &mips_io_port_base = base;
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->arch.io_port_base = base;
barrier();
}
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- * Linus
- *
- */
+#else /* !CONFIG_DYNAMIC_IO_PORT_BASE */
-#define __SLOW_DOWN_IO \
- __asm__ __volatile__( \
- "sb\t$0,0x80(%0)" \
- : : "r" (mips_io_port_base));
+static inline ulong mips_io_port_base(void)
+{
+ return 0;
+}
-#ifdef CONF_SLOWDOWN_IO
-#ifdef REALLY_SLOW_IO
-#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
-#else
-#define SLOW_DOWN_IO __SLOW_DOWN_IO
-#endif
-#else
-#define SLOW_DOWN_IO
-#endif
+static inline void set_io_port_base(unsigned long base)
+{
+ BUG_ON(base);
+}
+
+#endif /* !CONFIG_DYNAMIC_IO_PORT_BASE */
/*
* virt_to_phys - map virtual addresses to physical
#ifdef CONFIG_64BIT
if (addr < CKSEG0)
return XPHYSADDR(addr);
-
- return CPHYSADDR(addr);
-#else
- return addr - PAGE_OFFSET + PHYS_OFFSET;
#endif
+ return CPHYSADDR(addr);
}
+#define virt_to_phys virt_to_phys
/*
* phys_to_virt - map physical address to virtual
{
return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}
+#define phys_to_virt phys_to_virt
/*
* ISA I/O bus memory addresses are 1:1 with the physical address.
return pfx##ioswab##bwlq(__mem, __val); \
}
-#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p) \
\
static inline void pfx##out##bwlq##p(type val, unsigned long port) \
{ \
\
war_octeon_io_reorder_wmb(); \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
\
__val = pfx##ioswab##bwlq(__addr, val); \
\
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
*__addr = __val; \
- slow; \
} \
\
static inline type pfx##in##bwlq##p(unsigned long port) \
volatile type *__addr; \
type __val; \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
\
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
__val = *__addr; \
- slow; \
\
return pfx##ioswab##bwlq(__addr, __val); \
}
BUILDIO_MEM(q, u64)
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
- __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
- __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p)
#define BUILDIO_IOPORT(bwlq, type) \
__BUILD_IOPORT_PFX(, bwlq, type) \
*/
#define sync() mmiowb()
-#define MAP_NOCACHE (1)
-#define MAP_WRCOMBINE (0)
-#define MAP_WRBACK (0)
-#define MAP_WRTHROUGH (0)
+#define MAP_NOCACHE 1
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
if (flags == MAP_NOCACHE)
return ioremap(paddr, len);
- return (void *)paddr;
+ return (void *)CKSEG0ADDR(paddr);
}
+#define map_physmem map_physmem
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
+#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
}
+#define __BUILD_SETBITS(bwlq, sfx, end, type) \
+ \
+static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
+ type clr, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+__BUILD_CLRBITS(bwlq, sfx, end, type) \
+__BUILD_SETBITS(bwlq, sfx, end, type) \
+__BUILD_CLRSETBITS(bwlq, sfx, end, type)
+
+#define __to_cpu(v) (v)
+#define cpu_to__(v) (v)
+
+BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, le16, u16)
+BUILD_CLRSETBITS(w, be16, be16, u16)
+BUILD_CLRSETBITS(w, 16, _, u16)
+BUILD_CLRSETBITS(l, le32, le32, u32)
+BUILD_CLRSETBITS(l, be32, be32, u32)
+BUILD_CLRSETBITS(l, 32, _, u32)
+BUILD_CLRSETBITS(q, le64, le64, u64)
+BUILD_CLRSETBITS(q, be64, be64, u64)
+BUILD_CLRSETBITS(q, 64, _, u64)
+
+#include <asm-generic/io.h>
+
#endif /* _ASM_IO_H */
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