MIPS: Split I & D cache line size config

[u-boot] / arch / mips / lib / cache.c

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index e245614d1688e22cf325e2f8eaa4c79ca39a0fa3..19a42ff8316fec3168f2fc457a8ec01201977598 100644 (file)
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,25 +9,15 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-
 static inline unsigned long icache_line_size(void)
 {
-       return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
-       return CONFIG_SYS_CACHELINE_SIZE;
-}
+       unsigned long conf1, il;
 
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+       if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+               return CONFIG_SYS_ICACHE_LINE_SIZE;
 
-static inline unsigned long icache_line_size(void)
-{
-       unsigned long conf1, il;
        conf1 = read_c0_config1();
-       il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
+       il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
        if (!il)
                return 0;
        return 2 << il;
@@ -36,15 +26,17 @@ static inline unsigned long icache_line_size(void)
 static inline unsigned long dcache_line_size(void)
 {
        unsigned long conf1, dl;
+
+       if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+               return CONFIG_SYS_DCACHE_LINE_SIZE;
+
        conf1 = read_c0_config1();
-       dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
+       dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
        if (!dl)
                return 0;
        return 2 << dl;
 }
 
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
-
 void flush_cache(ulong start_addr, ulong size)
 {
        unsigned long ilsize = icache_line_size();
@@ -95,6 +87,10 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        const void *addr = (const void *)(start_addr & ~(lsize - 1));
        const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
+       /* aend will be miscalculated when size is zero, so we return here */
+       if (start_addr == stop)
+               return;
+
        while (1) {
                mips_cache(HIT_WRITEBACK_INV_D, addr);
                if (addr == aend)
@@ -109,6 +105,10 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        const void *addr = (const void *)(start_addr & ~(lsize - 1));
        const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
+       /* aend will be miscalculated when size is zero, so we return here */
+       if (start_addr == stop)
+               return;
+
        while (1) {
                mips_cache(HIT_INVALIDATE_D, addr);
                if (addr == aend)