mmc: reworked version lookup in mmc_startup_v4

[u-boot] / arch / mips / mach-ath79 / reset.c

diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 188eccb9bfebae195d51c8837d19b2484181884d..0593ec4a1b0dacc59e903b1317e868212581e7f1 100644 (file)
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
 #include <asm/types.h>
@@ -45,7 +45,7 @@ void _machine_restart(void)
                /* NOP */;
 }
 
-u32 get_bootstrap(void)
+u32 ath79_get_bootstrap(void)
 {
        void __iomem *base;
        u32 reg = 0;
@@ -81,14 +81,15 @@ static int eth_init_ar933x(void)
                                          MAP_NOCACHE);
        const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
                         AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
-                        AR933X_RESET_ETH_SWITCH;
+                        AR933X_RESET_ETH_SWITCH |
+                        AR933X_RESET_ETH_SWITCH_ANALOG;
 
        /* Clear MDIO slave EN bit. */
        clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
        mdelay(10);
 
        /* Get Atheros S26 PHY out of reset. */
-       clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+       clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
                        0x1f, 0x10);
        mdelay(10);
 
@@ -135,6 +136,23 @@ static int eth_init_ar934x(void)
        return 0;
 }
 
+static int eth_init_qca953x(void)
+{
+       void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+                                         MAP_NOCACHE);
+       const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+                        QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+                        QCA953X_RESET_ETH_SWITCH_ANALOG |
+                        QCA953X_RESET_ETH_SWITCH;
+
+       setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+       mdelay(1);
+       clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+       mdelay(1);
+
+       return 0;
+}
+
 int ath79_eth_reset(void)
 {
        /*
@@ -145,6 +163,8 @@ int ath79_eth_reset(void)
                return eth_init_ar933x();
        if (soc_is_ar934x())
                return eth_init_ar934x();
+       if (soc_is_qca953x())
+               return eth_init_qca953x();
 
        return -EINVAL;
 }
@@ -184,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
        return 0;
 }
 
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+       void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+                                         MAP_NOCACHE);
+
+       clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+                       0xf00, 0x200);
+       mdelay(10);
+
+       /* Ungate the USB block */
+       setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+                    QCA953X_RESET_USBSUS_OVERRIDE);
+       mdelay(1);
+       clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+                    QCA953X_RESET_USB_PHY);
+       mdelay(1);
+       clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+                    QCA953X_RESET_USB_PHY_ANALOG);
+       mdelay(1);
+       clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+                    QCA953X_RESET_USB_HOST);
+       mdelay(1);
+       clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+                    QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+       mdelay(1);
+
+       return 0;
+}
+
 int ath79_usb_reset(void)
 {
        void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
@@ -203,6 +252,8 @@ int ath79_usb_reset(void)
                return usb_reset_ar933x(reset_regs);
        if (soc_is_ar934x())
                return usb_reset_ar934x(reset_regs);
+       if (soc_is_qca953x())
+               return usb_reset_qca953x(reset_regs);
 
        return -EINVAL;
 }