/*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
SCCR_PCICM |
#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
+ SCCR_PCIEXP1CM |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
+ SCCR_PCIEXP2CM |
+#endif
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
SCCR_TSECCM |
#endif
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
+ (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
+ (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
+#endif
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
- gd->reset_status = __raw_readl(&im->reset.rsr);
+ gd->arch.reset_status = __raw_readl(&im->reset.rsr);
__raw_writel(~(RSR_RES), &im->reset.rsr);
/* AER - Arbiter Event Register - store status */
- gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
- gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
+ gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+ gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
/*
* RMR - Reset Mode Register
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
- clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
- __raw_readl(&im->lbus.lcrr);
+ clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
+ __raw_readl(&im->im_lbc.lcrr);
isync();
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
#ifdef CONFIG_SYS_SICRL
__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
+#ifdef CONFIG_SYS_GPR1
+ __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
/* Config QE ioports */
config_qe_ioports();
#endif
+ /* Set up preliminary BR/OR regs */
+ init_early_memctl_regs();
- /*
- * Memory Controller:
- */
-
- /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
- * addresses - these have to be modified later when FLASH size
- * has been determined
- */
-
-#if defined(CONFIG_SYS_BR0_PRELIM) \
- && defined(CONFIG_SYS_OR0_PRELIM) \
- && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
- && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
- im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
- im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
+ /* Local Access window setup */
+#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
-#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
+#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
- im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
- im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
- im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
- im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
- im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
- im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
- im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
-#ifdef CONFIG_USB_EHCI_FSL
-#ifndef CONFIG_MPC834x
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
uint32_t temp;
- struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+ struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
/* Configure interface. */
setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
-#endif
}
int cpu_init_r (void)
"reserved"
};
- int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
- >> AEATR_EVENT_SHIFT;
- int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
- >> AEATR_MSTR_ID_SHIFT;
- int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
- >> AEATR_TBST_SHIFT;
- int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
- >> AEATR_TSIZE_SHIFT;
- int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
- >> AEATR_TTYPE_SHIFT;
-
- if (!force && !gd->arbiter_event_address)
+ int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
+ >> AEATR_EVENT_SHIFT;
+ int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
+ >> AEATR_MSTR_ID_SHIFT;
+ int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
+ >> AEATR_TBST_SHIFT;
+ int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
+ >> AEATR_TSIZE_SHIFT;
+ int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
+ >> AEATR_TTYPE_SHIFT;
+
+ if (!force && !gd->arch.arbiter_event_address)
return 0;
puts("Arbiter Event Status:\n");
- printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
+ printf(" Event Address: 0x%08lX\n",
+ gd->arch.arbiter_event_address);
printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
- return gd->arbiter_event_address;
+ return gd->arch.arbiter_event_address;
}
#elif defined(CONFIG_DISPLAY_AER_BRIEF)
static int print_83xx_arb_event(int force)
{
- if (!force && !gd->arbiter_event_address)
+ if (!force && !gd->arch.arbiter_event_address)
return 0;
printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
- gd->arbiter_event_attributes, gd->arbiter_event_address);
+ gd->arch.arbiter_event_attributes,
+ gd->arch.arbiter_event_address);
- return gd->arbiter_event_address;
+ return gd->arch.arbiter_event_address;
}
#endif /* CONFIG_DISPLAY_AER_xxxx */
RSR_HRS, "External/Internal Hard"}
};
static int n = sizeof bits / sizeof bits[0];
- ulong rsr = gd->reset_status;
+ ulong rsr = gd->arch.reset_status;
int i;
char *sep;