Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

[u-boot] / arch / powerpc / cpu / mpc83xx / start.S

diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index a7c80792ded4dc54f6e87a73421be44b11b88140..b70b4ca12cea1540a4697654b1e41a527eb1078c 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -27,9 +27,12 @@
  *  U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc83xx.h>
-#include <timestamp.h>
+#ifndef  CONFIG_IDENT_STRING
+#define  CONFIG_IDENT_STRING "MPC83XX"
+#endif
 #include <version.h>
 
 #define CONFIG_83XX    1               /* needed for Linux kernel header files*/
@@ -40,10 +43,7 @@
 
 #include <asm/cache.h>
 #include <asm/mmu.h>
-
-#ifndef  CONFIG_IDENT_STRING
-#define  CONFIG_IDENT_STRING "MPC83XX"
-#endif
+#include <asm/u-boot.h>
 
 /* We don't want the  MMU yet.
  */
@@ -70,7 +70,7 @@
        START_GOT
        GOT_ENTRY(_GOT2_TABLE_)
        GOT_ENTRY(__bss_start)
-       GOT_ENTRY(_end)
+       GOT_ENTRY(__bss_end__)
 
 #ifndef CONFIG_NAND_SPL
        GOT_ENTRY(_FIXUP_TABLE_)
@@ -105,9 +105,7 @@
 
        .globl  version_string
 version_string:
-       .ascii U_BOOT_VERSION
-       .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
-       .ascii " ", CONFIG_IDENT_STRING, "\0"
+       .ascii U_BOOT_VERSION_STRING, "\0"
 
        .align 2
 
@@ -183,22 +181,9 @@ ppcDWload:
 
        .globl  _start
 _start: /* time t 0 */
-       li      r21, BOOTFLAG_COLD  /* Normal Power-On: Boot from FLASH*/
-       nop
-       b       boot_cold
-
-       . = EXC_OFF_SYS_RESET + 0x10
-
-       .globl  _start_warm
-_start_warm:
-       li      r21, BOOTFLAG_WARM      /* Software reboot      */
-       b       boot_warm
-
-
-boot_cold: /* time t 3 */
        lis     r4, CONFIG_DEFAULT_IMMR@h
        nop
-boot_warm: /* time t 5 */
+
        mfmsr   r5                      /* save msr contents    */
 
        /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
@@ -302,11 +287,11 @@ in_flash:
        /* run low-level CPU init code (in Flash)*/
        bl      cpu_init_f
 
-       /* r3: BOOTFLAG */
-       mr      r3, r21
        /* run 1st part of board init code (in Flash)*/
        bl      board_init_f
 
+       /* NOTREACHED - board_init_f() does not return */
+
 #ifndef CONFIG_NAND_SPL
 /*
  * Vector Table
@@ -507,7 +492,7 @@ init_e300_core: /* time t 10 */
 
        lis     r3, CONFIG_SYS_IMMR@h
 #if defined(CONFIG_WATCHDOG)
-       /* Initialise the Wathcdog values and reset it (if req) */
+       /* Initialise the Watchdog values and reset it (if req) */
        /*------------------------------------------------------*/
        lis r4, CONFIG_SYS_WATCHDOG_VALUE
        ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
@@ -520,7 +505,7 @@ init_e300_core: /* time t 10 */
        li      r4, -0x55C7
        sth     r4, SWSRR@l(r3)
 #else
-       /* Disable Wathcdog  */
+       /* Disable Watchdog  */
        /*-------------------*/
        lwz r4, SWCRR(r3)
        /* Check to see if its enabled for disabling
@@ -739,6 +724,7 @@ setup_bats:
  * Note: requires that all cache bits in
  * HID0 are in the low half word.
  */
+#ifndef CONFIG_NAND_SPL
        .globl  icache_enable
 icache_enable:
        mfspr   r3, HID0
@@ -767,6 +753,7 @@ icache_status:
        mfspr   r3, HID0
        rlwinm  r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
        blr
+#endif /* !CONFIG_NAND_SPL */
 
        .globl  dcache_enable
 dcache_enable:
@@ -962,10 +949,12 @@ in_ram:
        beq     4f
 3:     lwzu    r4,4(r3)
        lwzux   r0,r4,r11
+       cmpwi   r0,0
        add     r0,r0,r11
-       stw     r10,0(r3)
+       stw     r4,0(r3)
+       beq-    5f
        stw     r0,0(r4)
-       bdnz    3b
+5:     bdnz    3b
 4:
 #endif
 
@@ -984,7 +973,7 @@ clear_bss:
         */
        lwz     r4,GOT(environment)
 #else
-       lwz     r4,GOT(_end)
+       lwz     r4,GOT(__bss_end__)
 #endif
 
        cmplw   0, r3, r4
@@ -1080,7 +1069,7 @@ lock_ram_in_cache:
         */
        lis     r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
        ori     r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-       li      r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+       li      r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
                     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
        mtctr   r4
 1:
@@ -1102,7 +1091,7 @@ unlock_ram_in_cache:
        /* invalidate the INIT_RAM section */
        lis     r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
        ori     r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-       li      r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+       li      r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
                     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
        mtctr   r4
 1:     icbi    r0, r3
@@ -1165,6 +1154,10 @@ map_flash_by_law1:
        bne 1b
 
        stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
+       /* Wait for HW to catch up */
+       lwz r4, LBLAWAR1(r3)
+       twi 0,r4,0
+       isync
        blr
 
        /* Though all the LBIU Local Access Windows and LBC Banks will be
@@ -1203,5 +1196,9 @@ remap_flash_by_law0:
        xor r4, r4, r4
        stw r4, LBLAWBAR1(r3)
        stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
+       /* Wait for HW to catch up */
+       lwz r4, LBLAWAR1(r3)
+       twi 0,r4,0
+       isync
        blr
 #endif /* CONFIG_SYS_FLASHBOOT */