bool "Support kmp204x"
select ARCH_P2041
select PHYS_64BIT
+ imply CMD_CRAMFS
config TARGET_XPEDITE520X
bool "Support xpedite520x"
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_B4860
bool
select SYS_FSL_ERRATUM_A007075
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_BSC9131
bool
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_IFC
config ARCH_BSC9132
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_IFC
config ARCH_C29X
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_6
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_IFC
config ARCH_MPC8536
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_MPC8540
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_MPC8548
bool
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
+ select FSL_ELBC
config ARCH_MPC8572
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1010
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_IFC
config ARCH_P1011
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1020
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1021
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1022
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1023
bool
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P1024
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1025
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P2020
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P2041
bool
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P3041
bool
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P4080
bool
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P5020
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_ELBC
config ARCH_P5040
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_ELBC
config ARCH_QEMU_E500
bool
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T1024
bool
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T1040
bool
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T1042
bool
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T2080
bool
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A007815
+ select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_T2081
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_T4160
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_T4240
bool
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A007815
+ select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config BOOKE
bool
config SYS_FSL_ERRATUM_A007212
bool
+config SYS_FSL_ERRATUM_A007815
+ bool
+
config SYS_FSL_ERRATUM_A007798
bool
+config SYS_FSL_ERRATUM_A007907
+ bool
+
config SYS_FSL_ERRATUM_A008044
bool
config SYS_PPC_E500_USE_DEBUG_TLB
bool
+config FSL_IFC
+ bool
+
+config FSL_ELBC
+ bool
+
config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB
symbol should be set to the TLB1 entry to be used for this
purpose. If unsure, do not change.
+config SYS_FSL_IFC_CLK_DIV
+ int "Divider of platform clock"
+ depends on FSL_IFC
+ default 2 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_T1024 || \
+ ARCH_T1023 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 1
+ help
+ Defines divider of platform clock(clock input to
+ IFC controller).
+
+config SYS_FSL_LBC_CLK_DIV
+ int "Divider of platform clock"
+ depends on FSL_ELBC || ARCH_MPC8540 || \
+ ARCH_MPC8548 || ARCH_MPC8541 || \
+ ARCH_MPC8555 || ARCH_MPC8560 || \
+ ARCH_MPC8568
+
+ default 2 if ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040
+ default 1
+
+ help
+ Defines divider of platform clock(clock input to
+ eLBC controller).
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
projects / u-boot / blobdiff