powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536

[u-boot] / arch / powerpc / cpu / mpc85xx / cpu.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f5b39c067c73843e1aeeacdea3fd392bc9d1700f..49c0551692985ebca9bc9fe0fc26dfd15acb5196 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -46,7 +46,6 @@ int checkcpu (void)
 {
        sys_info_t sysinfo;
        uint pvr, svr;
-       uint fam;
        uint ver;
        uint major, minor;
        struct cpu_type *cpu;
@@ -65,13 +64,11 @@ int checkcpu (void)
        u32 ddr_ratio = 0;
 #endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
-       int i;
+       unsigned int i, core, nr_cores = cpu_numcores();
+       u32 mask = cpu_mask();
 
        svr = get_svr();
        major = SVR_MAJ(svr);
-#ifdef CONFIG_MPC8536
-       major &= 0x7; /* the msb of this nibble is a mfg code */
-#endif
        minor = SVR_MIN(svr);
 
        if (cpu_numcores() > 1) {
@@ -94,30 +91,25 @@ int checkcpu (void)
        printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
 
        pvr = get_pvr();
-       fam = PVR_FAM(pvr);
        ver = PVR_VER(pvr);
        major = PVR_MAJ(pvr);
        minor = PVR_MIN(pvr);
 
        printf("Core:  ");
-       if (PVR_FAM(PVR_85xx)) {
-               switch(PVR_MEM(pvr)) {
-               case 0x1:
-               case 0x2:
-                       puts("E500");
-                       break;
-               case 0x3:
-                       puts("E500MC");
-                       break;
-               case 0x4:
-                       puts("E5500");
-                       break;
-               default:
-                       puts("Unknown");
-                       break;
-               }
-       } else {
+       switch(ver) {
+       case PVR_VER_E500_V1:
+       case PVR_VER_E500_V2:
+               puts("E500");
+               break;
+       case PVR_VER_E500MC:
+               puts("E500MC");
+               break;
+       case PVR_VER_E5500:
+               puts("E5500");
+               break;
+       default:
                puts("Unknown");
+               break;
        }
 
        printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
@@ -125,11 +117,11 @@ int checkcpu (void)
        get_sys_info(&sysinfo);
 
        puts("Clock Configuration:");
-       for (i = 0; i < cpu_numcores(); i++) {
+       for_each_cpu(i, core, nr_cores, mask) {
                if (!(i & 3))
                        printf ("\n       ");
-               printf("CPU%d:%-4s MHz, ",
-                               i,strmhz(buf1, sysinfo.freqProcessor[i]));
+               printf("CPU%d:%-4s MHz, ", core,
+                       strmhz(buf1, sysinfo.freqProcessor[core]));
        }
        printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
@@ -234,13 +226,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 /*
  * Get timebase clock frequency
  */
+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif
 unsigned long get_tbclk (void)
 {
-#ifdef CONFIG_FSL_CORENET
-       return (gd->bus_clk + 8) / 16;
-#else
-       return (gd->bus_clk + 4UL)/8UL;
-#endif
+       unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
+
+       return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
 }
 
 
@@ -335,7 +328,9 @@ phys_size_t initdram(int board_type)
        }
 #endif
 
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if    defined(CONFIG_SPD_EEPROM)      || \
+       defined(CONFIG_DDR_SPD)         || \
+       defined(CONFIG_SYS_DDR_RAW_TIMING)
        dram_size = fsl_ddr_sdram();
 #else
        dram_size = fixed_sdram();
@@ -355,7 +350,7 @@ phys_size_t initdram(int board_type)
        lbc_sdram_init();
 #endif
 
-       puts("DDR: ");
+       debug("DDR: ");
        return dram_size;
 }
 #endif /* CONFIG_SYS_RAMBOOT */
@@ -371,6 +366,8 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 unsigned int
        setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
 
+void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
+
 static void dump_spd_ddr_reg(void)
 {
        int i, j, k, m;
@@ -457,19 +454,9 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
        u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
        unsigned long epn;
        u32 tsize, valid, ptr;
-       phys_addr_t rpn = 0;
        int ddr_esel;
 
-       ptr = vstart;
-
-       while (ptr < (vstart + size)) {
-               ddr_esel = find_tlb_idx((void *)ptr, 1);
-               if (ddr_esel != -1) {
-                       read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
-                       disable_tlb(ddr_esel);
-               }
-               ptr += TSIZE_TO_BYTES(tsize);
-       }
+       clear_ddr_tlbs_phys(p_addr, size>>20);
 
        /* Setup new tlb to cover the physical address */
        setup_ddr_tlbs_phys(p_addr, size>>20);