GCC4.6: Squash warnings in denali_spd_ddr2.c

[u-boot] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 8ece970097246c2fe1b102935ad78b439fe7ce3a..0a4ce538f3b3494bd262af16234d30fec21ca0f3 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -31,12 +31,17 @@
 #include <asm/processor.h>
 #include <ioports.h>
 #include <sata.h>
+#include <fm_eth.h>
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include "mp.h"
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include <nand.h>
+#include <errno.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -141,6 +146,22 @@ static void enable_cpc(void)
        for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
                u32 cpccfg0 = in_be32(&cpc->cpccfg0);
                size += CPC_CFG0_SZ_K(cpccfg0);
+#ifdef CONFIG_RAMBOOT_PBL
+               if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
+                       /* find and disable LAW of SRAM */
+                       struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+                       if (law.index == -1) {
+                               printf("\nFatal error happened\n");
+                               return;
+                       }
+                       disable_law(law.index);
+
+                       clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+                       out_be32(&cpc->cpccsr0, 0);
+                       out_be32(&cpc->cpcsrcr0, 0);
+               }
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
                setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
@@ -164,6 +185,9 @@ void invalidate_cpc(void)
        cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
        for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+               /* skip CPC when it used as all SRAM */
+               if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
+                       continue;
                /* Flash invalidate the CPC and clear all the locks */
                out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
                while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
@@ -199,6 +223,12 @@ static void corenet_tb_init(void)
 void cpu_init_f (void)
 {
        extern void m8560_cpm_reset (void);
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+#if defined(CONFIG_SECURE_BOOT)
+       struct law_entry law;
+#endif
 #ifdef CONFIG_MPC8548
        ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
        uint svr = get_svr();
@@ -216,6 +246,13 @@ void cpu_init_f (void)
        disable_tlb(14);
        disable_tlb(15);
 
+#if defined(CONFIG_SECURE_BOOT)
+       /* Disable the LAW created for NOR flash by the PBI commands */
+       law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+       if (law.index != -1)
+               disable_law(law.index);
+#endif
+
 #ifdef CONFIG_CPM2
        config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 #endif
@@ -239,6 +276,13 @@ void cpu_init_f (void)
 
        /* Invalidate the CPC before DDR gets enabled */
        invalidate_cpc();
+
+ #ifdef CONFIG_SYS_DCSRBAR_PHYS
+       /* set DCSRCR so that DCSR space is 1G */
+       setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
+       in_be32(&gur->dcsrcr);
+#endif
+
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */
@@ -358,6 +402,12 @@ int cpu_init_r(void)
                puts("enabled\n");
        }
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
+       if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+           (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+               puts("N/A\n");
+               goto skip_l2;
+       }
+
        u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 
        /* invalidate the L2 cache */
@@ -378,18 +428,14 @@ int cpu_init_r(void)
                        ;
                printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
        }
+
+skip_l2:
 #else
        puts("disabled\n");
 #endif
 
        enable_cpc();
 
-#ifdef CONFIG_QE
-       uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
-       qe_init(qe_base);
-       qe_reset();
-#endif
-
        /* needs to be in ram since code uses global static vars */
        fsl_serdes_init();
 
@@ -417,6 +463,30 @@ int cpu_init_r(void)
        clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
        __raw_readl(&lbc->lcrr);
        isync();
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+       udelay(100);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
+       {
+               ccsr_usb_phy_t *usb_phy1 =
+                       (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+               out_be32(&usb_phy1->usb_enable_override,
+                               CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+       }
+#endif
+#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
+       {
+               ccsr_usb_phy_t *usb_phy2 =
+                       (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+               out_be32(&usb_phy2->usb_enable_override,
+                               CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+       }
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+       fman_enet_init();
 #endif
 
        return 0;
@@ -449,3 +519,25 @@ int sata_initialize(void)
        return 1;
 }
 #endif
+
+void cpu_secondary_init_r(void)
+{
+#ifdef CONFIG_QE
+       uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+       int ret;
+       size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+
+       /* load QE firmware from NAND flash to DDR first */
+       ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+                       &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+
+       if (ret && ret == -EUCLEAN) {
+               printf ("NAND read for QE firmware at offset %x failed %d\n",
+                               CONFIG_SYS_QE_FW_IN_NAND, ret);
+       }
+#endif
+       qe_init(qe_base);
+       qe_reset();
+#endif
+}