Merge branch 'master' of /home/wd/git/u-boot/custodians

[u-boot] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b3da970d4201bb34ed29d20f49080266cb56e20c..2e4a06c35abed3d997695bb83463c3cb1bba2ac5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -31,17 +31,21 @@
 #include <asm/processor.h>
 #include <ioports.h>
 #include <sata.h>
+#include <fm_eth.h>
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
+#include <linux/compiler.h>
 #include "mp.h"
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
 #endif
 
+#include "../../../../drivers/block/fsl_sata.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void srio_init(void);
@@ -222,6 +226,12 @@ static void corenet_tb_init(void)
 void cpu_init_f (void)
 {
        extern void m8560_cpm_reset (void);
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+#if defined(CONFIG_SECURE_BOOT)
+       struct law_entry law;
+#endif
 #ifdef CONFIG_MPC8548
        ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
        uint svr = get_svr();
@@ -239,6 +249,13 @@ void cpu_init_f (void)
        disable_tlb(14);
        disable_tlb(15);
 
+#if defined(CONFIG_SECURE_BOOT)
+       /* Disable the LAW created for NOR flash by the PBI commands */
+       law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+       if (law.index != -1)
+               disable_law(law.index);
+#endif
+
 #ifdef CONFIG_CPM2
        config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 #endif
@@ -262,6 +279,13 @@ void cpu_init_f (void)
 
        /* Invalidate the CPC before DDR gets enabled */
        invalidate_cpc();
+
+ #ifdef CONFIG_SYS_DCSRBAR_PHYS
+       /* set DCSRCR so that DCSR space is 1G */
+       setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
+       in_be32(&gur->dcsrcr);
+#endif
+
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */
@@ -280,6 +304,7 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
  */
 int cpu_init_r(void)
 {
+       __maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_SYS_LBC_LCRR
        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
@@ -295,11 +320,9 @@ int cpu_init_r(void)
 #if defined(CONFIG_L2_CACHE)
        volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
        volatile uint cache_ctl;
-       uint svr, ver;
-       uint l2srbar;
+       uint ver;
        u32 l2siz_field;
 
-       svr = get_svr();
        ver = SVR_SOC_VER(svr);
 
        asm("msync;isync");
@@ -364,8 +387,8 @@ int cpu_init_r(void)
 
        if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
                puts("already enabled");
-               l2srbar = l2cache->l2srbar0;
 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+               u32 l2srbar = l2cache->l2srbar0;
                if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
                                && l2srbar >= CONFIG_SYS_FLASH_BASE) {
                        l2srbar = CONFIG_SYS_INIT_L2_ADDR;
@@ -381,6 +404,12 @@ int cpu_init_r(void)
                puts("enabled\n");
        }
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
+       if ((SVR_SOC_VER(svr) == SVR_P2040) ||
+           (SVR_SOC_VER(svr) == SVR_P2040_E)) {
+               puts("N/A\n");
+               goto skip_l2;
+       }
+
        u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 
        /* invalidate the L2 cache */
@@ -401,6 +430,8 @@ int cpu_init_r(void)
                        ;
                printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
        }
+
+skip_l2:
 #else
        puts("disabled\n");
 #endif
@@ -434,6 +465,9 @@ int cpu_init_r(void)
        clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
        __raw_readl(&lbc->lcrr);
        isync();
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+       udelay(100);
+#endif
 #endif
 
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
@@ -453,6 +487,36 @@ int cpu_init_r(void)
        }
 #endif
 
+#ifdef CONFIG_FMAN_ENET
+       fman_enet_init();
+#endif
+
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+       /*
+        * For P1022/1013 Rev1.0 silicon, after power on SATA host
+        * controller is configured in legacy mode instead of the
+        * expected enterprise mode. Software needs to clear bit[28]
+        * of HControl register to change to enterprise mode from
+        * legacy mode.  We assume that the controller is offline.
+        */
+       if (IS_SVR_REV(svr, 1, 0) &&
+           ((SVR_SOC_VER(svr) == SVR_P1022) ||
+            (SVR_SOC_VER(svr) == SVR_P1022_E) ||
+            (SVR_SOC_VER(svr) == SVR_P1013) ||
+            (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+               fsl_sata_reg_t *reg;
+
+               /* first SATA controller */
+               reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+               clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
+
+               /* second SATA controller */
+               reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+               clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
+       }
+#endif
+
+
        return 0;
 }
 
@@ -488,17 +552,17 @@ void cpu_secondary_init_r(void)
 {
 #ifdef CONFIG_QE
        uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
        int ret;
-       size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+       size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
 
        /* load QE firmware from NAND flash to DDR first */
-       ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
-                       &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+       ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
+                       &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
 
        if (ret && ret == -EUCLEAN) {
                printf ("NAND read for QE firmware at offset %x failed %d\n",
-                               CONFIG_SYS_QE_FW_IN_NAND, ret);
+                               CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
        }
 #endif
        qe_init(qe_base);