]> git.sur5r.net Git - u-boot/blobdiff - arch/powerpc/cpu/mpc85xx/cpu_init.c
cosmetic: delete misleading comment /* CONFIG_BOARDDIR */
[u-boot] / arch / powerpc / cpu / mpc85xx / cpu_init.c
index 867abb6cf73038a1ef3d0bb05eadcf7c02a0ab15..36ef23232ed044db5cf3316067b445d213c0f87a 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+       sys_info_t sysinfo;
+
+       get_sys_info(&sysinfo);
+       if (sysinfo.diff_sysclk == 1) {
+               clrbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+               setbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+               }
+}
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
 {
@@ -815,6 +838,9 @@ skip_l2:
                             CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
                             CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
                             CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+               usb_single_source_clk_configure(usb_phy);
+#endif
                setbits_be32(&usb_phy->port1.ctrl,
                             CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
                setbits_be32(&usb_phy->port1.drvvbuscfg,
@@ -899,19 +925,6 @@ void cpu_secondary_init_r(void)
 #endif
 
 #ifdef CONFIG_QE
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
-       int ret;
-       size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
-
-       /* load QE firmware from NAND flash to DDR first */
-       ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
-                       &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
-
-       if (ret && ret == -EUCLEAN) {
-               printf ("NAND read for QE firmware at offset %x failed %d\n",
-                               CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
-       }
-#endif
        qe_init(qe_base);
        qe_reset();
 #endif