cosmetic: delete misleading comment /* CONFIG_BOARDDIR */

[u-boot] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index a2b79cc7cc0fd153ea7c5e319b357d7d1c1721a8..36ef23232ed044db5cf3316067b445d213c0f87a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -39,6 +39,29 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+       sys_info_t sysinfo;
+
+       get_sys_info(&sysinfo);
+       if (sysinfo.diff_sysclk == 1) {
+               clrbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+               setbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+               }
+}
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
 {
@@ -815,6 +838,9 @@ skip_l2:
                             CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
                             CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
                             CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+               usb_single_source_clk_configure(usb_phy);
+#endif
                setbits_be32(&usb_phy->port1.ctrl,
                             CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
                setbits_be32(&usb_phy->port1.drvvbuscfg,