/*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
#include <ioports.h>
#include <sata.h>
#include <asm/io.h>
+#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_MPC8536
-extern void fsl_serdes_init(void);
-#endif
+extern void srio_init(void);
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
}
#endif
+#ifdef CONFIG_SYS_FSL_CPC
+static void enable_cpc(void)
+{
+ int i;
+ u32 size = 0;
+
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+ for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+ u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+ size += CPC_CFG0_SZ_K(cpccfg0);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
+ setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
+ setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
+#endif
+
+ out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
+ /* Read back to sync write */
+ in_be32(&cpc->cpccsr0);
+
+ }
+
+ printf("Corenet Platform Cache: %d KB enabled\n", size);
+}
+
+void invalidate_cpc(void)
+{
+ int i;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+ for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+ /* Flash invalidate the CPC and clear all the locks */
+ out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
+ while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
+ ;
+ }
+}
+#else
+#define enable_cpc()
+#define invalidate_cpc()
+#endif /* CONFIG_SYS_FSL_CPC */
+
/*
* Breathe some life into the CPU...
*
volatile ccsr_rcpm_t *rcpm =
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
- (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */
/* Config QE ioports */
config_qe_ioports();
#endif
-#if defined(CONFIG_MPC8536)
- fsl_serdes_init();
-#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
corenet_tb_init();
#endif
init_used_tlb_cams();
+
+ /* Invalidate the CPC before DDR gets enabled */
+ invalidate_cpc();
}
+/* Implement a dummy function for those platforms w/o SERDES */
+static void __fsl_serdes__init(void)
+{
+ return ;
+}
+__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
/*
* Initialize L2 as cache.
* use the same bit-encoding as the older 8555, etc, parts.
*
*/
-
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ flush_dcache();
+ mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+ sync();
+#endif
+
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
puts("already enabled");
l2srbar = l2cache->l2srbar0;
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
#else
puts("disabled\n");
#endif
+
+ enable_cpc();
+
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
qe_init(qe_base);
qe_reset();
#endif
+ /* needs to be in ram since code uses global static vars */
+ fsl_serdes_init();
+
+#ifdef CONFIG_SYS_SRIO
+ srio_init();
+#endif
+
#if defined(CONFIG_MP)
setup_mp();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+ {
+ void *p;
+ p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ setbits_be32(p, 1 << (31 - 14));
+ }
+#endif
+
#ifdef CONFIG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing