]> git.sur5r.net Git - u-boot/blobdiff - arch/powerpc/cpu/mpc85xx/cpu_init.c
powerpc:Add support of SPL non-relocation
[u-boot] / arch / powerpc / cpu / mpc85xx / cpu_init.c
index 941c20e00a58f2994d5859ca5cb4321ba249836d..a2b79cc7cc0fd153ea7c5e319b357d7d1c1721a8 100644 (file)
@@ -350,6 +350,7 @@ void cpu_init_f (void)
        extern void m8560_cpm_reset (void);
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
        struct law_entry law;
@@ -414,6 +415,13 @@ void cpu_init_f (void)
        in_be32(&gur->dcsrcr);
 #endif
 
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CONFIG_DEEP_SLEEP
+       /* disable the console if boot from deep sleep */
+       if (in_be32(&gur->scrtsr[0]) & (1 << 3))
+               gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
        fsl_erratum_a007212_workaround();
 #endif
@@ -891,19 +899,6 @@ void cpu_secondary_init_r(void)
 #endif
 
 #ifdef CONFIG_QE
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
-       int ret;
-       size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
-
-       /* load QE firmware from NAND flash to DDR first */
-       ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
-                       &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
-
-       if (ret && ret == -EUCLEAN) {
-               printf ("NAND read for QE firmware at offset %x failed %d\n",
-                               CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
-       }
-#endif
        qe_init(qe_base);
        qe_reset();
 #endif