board/t208x: update t2080qds/t2080rdb for errata A-007186

[u-boot] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index a2b79cc7cc0fd153ea7c5e319b357d7d1c1721a8..d6cf88555a11d23056caef9d62a58a9b436a2986 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -39,6 +39,29 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+       sys_info_t sysinfo;
+
+       get_sys_info(&sysinfo);
+       if (sysinfo.diff_sysclk == 1) {
+               clrbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+               setbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+               }
+}
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
 {
@@ -345,12 +368,12 @@ void fsl_erratum_a007212_workaround(void)
 }
 #endif
 
-void cpu_init_f (void)
+ulong cpu_init_f(void)
 {
+       ulong flag = 0;
        extern void m8560_cpm_reset (void);
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
        struct law_entry law;
@@ -419,13 +442,14 @@ void cpu_init_f (void)
 #ifdef CONFIG_DEEP_SLEEP
        /* disable the console if boot from deep sleep */
        if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-               gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+               flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
 #endif
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
        fsl_erratum_a007212_workaround();
 #endif
 
+       return flag;
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */
@@ -439,10 +463,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 int enable_cluster_l2(void)
 {
        int i = 0;
-       u32 cluster;
+       u32 cluster, svr = get_svr();
        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        struct ccsr_cluster_l2 __iomem *l2cache;
 
+       /* only the L2 of first cluster should be enabled as expected on T4080,
+        * but there is no EOC in the first cluster as HW sake, so return here
+        * to skip enabling L2 cache of the 2nd cluster.
+        */
+       if (SVR_SOC_VER(svr) == SVR_T4080)
+               return 0;
+
        cluster = in_be32(&gur->tp_cluster[i].lower);
        if (cluster & TP_CLUSTER_EOC)
                return 0;
@@ -815,6 +846,9 @@ skip_l2:
                             CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
                             CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
                             CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+               usb_single_source_clk_configure(usb_phy);
+#endif
                setbits_be32(&usb_phy->port1.ctrl,
                             CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
                setbits_be32(&usb_phy->port1.drvvbuscfg,
@@ -862,6 +896,7 @@ skip_l2:
        }
 #endif
 
+       init_used_tlb_cams();
 
        return 0;
 }