/* enable time base at the platform */
out_be32(&rcpm->ctbenrl, 0);
+
+ /* readback to sync write */
+ in_be32(&rcpm->ctbenrl);
+
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);
+
out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
else
devdisr |= MPC85xx_DEVDISR_TB0;
out_be32(&gur->devdisr, devdisr);
+
+ /* readback to sync write */
+ in_be32(&gur->devdisr);
+
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);