Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / powerpc / cpu / mpc85xx / p1022_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
index 52e109b1cf9483392196fc91d98226256339bbca..14d17eb51b81a51c134c8842e9175d383c3ee57f 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
@@ -2,10 +2,7 @@
  * Copyright 2010 Freescale Semiconductor, Inc.
  * Author: Timur Tabi <timur@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
@@ -17,6 +14,8 @@
 #define SRDS1_MAX_LANES                4
 #define SRDS2_MAX_LANES                2
 
+static u32 serdes1_prtcl_map, serdes2_prtcl_map;
+
 static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
        [0x00] = {NONE, NONE, NONE, NONE},
        [0x01] = {NONE, NONE, NONE, NONE},
@@ -71,96 +70,42 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
        [0x1f] = {NONE, NONE},
 };
 
-/*
- * A list of PCI and SATA slots
- */
-enum slot_id {
-       SLOT_PCIE1 = 1,
-       SLOT_PCIE2,
-       SLOT_PCIE3,
-       SLOT_PCIE4,
-       SLOT_PCIE5,
-       SLOT_SATA1,
-       SLOT_SATA2
-};
+int is_serdes_configured(enum srds_prtcl device)
+{
+       int ret = (1 << device) & serdes1_prtcl_map;
 
-/*
- * This array maps the slot identifiers to their names on the P1022DS board.
- */
-static const char *slot_names[] = {
-       [SLOT_PCIE1] = "Slot 1",
-       [SLOT_PCIE2] = "Slot 2",
-       [SLOT_PCIE3] = "Slot 3",
-       [SLOT_PCIE4] = "Slot 4",
-       [SLOT_PCIE5] = "Mini-PCIe",
-       [SLOT_SATA1] = "SATA 1",
-       [SLOT_SATA2] = "SATA 2",
-};
+       if (ret)
+               return ret;
 
-/*
- * This array maps a given SERDES configuration and SERDES device to the PCI or
- * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
- */
-static u8 serdes_dev_slot[][SATA2 + 1] = {
-       [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
-       [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-       [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
-                  [PCIE2] = SLOT_PCIE5 },
-       [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
-                  [PCIE2] = SLOT_PCIE3,
-                  [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-       [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
-                  [PCIE2] = SLOT_PCIE3 },
-       [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
-                  [PCIE2] = SLOT_PCIE3,
-                  [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-       [0x1c] = { [PCIE1] = SLOT_PCIE1,
-                  [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-       [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
-       [0x1f] = { [PCIE1] = SLOT_PCIE1 },
-};
+       return (1 << device) & serdes2_prtcl_map;
+}
 
-int is_serdes_configured(enum srds_prtcl device)
+void fsl_serdes_init(void)
 {
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-       unsigned int i;
+       int lane;
 
-       debug("%s: dev = %d\n", __FUNCTION__, device);
-       debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg);
+       debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
-               printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg);
-               return 0;
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
+               printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+               return;
        }
-
-       for (i = 0; i < SRDS1_MAX_LANES; i++) {
-               if (serdes1_cfg_tbl[srds_cfg][i] == device)
-                       return 1;
-               if (serdes2_cfg_tbl[srds_cfg][i] == device)
-                       return 1;
+       for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+               serdes1_prtcl_map |= (1 << lane_prtcl);
        }
 
-       return 0;
-}
-
-/*
- * Returns the name of the slot to which the PCIe or SATA controller is
- * connected
- */
-const char *serdes_slot_name(enum srds_prtcl device)
-{
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-       u32 pordevsr = in_be32(&gur->pordevsr);
-       unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-                               MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-       enum slot_id slot = serdes_dev_slot[srds_cfg][device];
-       const char *name = slot_names[slot];
+       if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
+               printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+               return;
+       }
 
-       if (name)
-               return name;
-       else
-               return "Nothing";
+       for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
+               serdes2_prtcl_map |= (1 << lane_prtcl);
+       }
 }