Merge branch 'master' of git://git.denx.de/u-boot-tegra

[u-boot] / arch / powerpc / cpu / mpc85xx / release.S

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 15bbbc15aa4ef27ae55e61ac24629880d0706804..a2c0ad4244ffc59644a90da7995965c300cf1ac2 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -10,8 +10,6 @@
 #include <mpc85xx.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1      /* avoid reading Linux autoconf.h file  */
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
@@ -226,6 +224,21 @@ __secondary_start_page:
 2:
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+       /*
+        * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
+        * write shadow mode. This code should run after other code setting
+        * DCWS.
+        */
+       mfspr   r3,L1CSR2
+       andis.  r3,r3,(L1CSR2_DCWS)@h
+       beq     1f
+       mfspr   r3, SPRN_HDBCR0
+       oris    r3, r3, 0x8000
+       mtspr   SPRN_HDBCR0, r3
+1:
+#endif
+
 #ifdef CONFIG_BACKSIDE_L2_CACHE
        /* skip L2 setup on P2040/P2040E as they have no L2 */
        mfspr   r3,SPRN_SVR
@@ -392,9 +405,6 @@ __second_half_boot_page:
        bne     3b
        isync
 
-       /* setup IVORs to match fixed offsets */
-#include "fixed_ivor.S"
-
        /* get the upper bits of the addr */
        lwz     r11,ENTRY_ADDR_UPPER(r10)