/*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
#include <common.h>
#include <ppc_asm.tmpl>
+#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ unsigned int cpu;
const u8 core_cplx_PLL[16] = {
[ 0] = 0, /* CC1 PPL / 1 */
[14] = 4, /* CC4 PPL / 4 */
};
uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+ uint ratio[4];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ uint mem_pll_rat;
sysInfo->freqSystemBus = sysclk;
sysInfo->freqDDRBus = sysclk;
- freqCC_PLL[0] = sysclk;
- freqCC_PLL[1] = sysclk;
- freqCC_PLL[2] = sysclk;
- freqCC_PLL[3] = sysclk;
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
- freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
- freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
- freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
- freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+ mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+ if (mem_pll_rat > 2)
+ sysInfo->freqDDRBus *= mem_pll_rat;
+ else
+ sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
+ ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+ ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+ ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+ ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+ for (i = 0; i < 4; i++) {
+ if (ratio[i] > 4)
+ freqCC_PLL[i] = sysclk * ratio[i];
+ else
+ freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
+ }
rcw_tmp = in_be32(&gur->rcwsr[3]);
- for (i = 0; i < cpu_numcores(); i++) {
- u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
+ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
- sysInfo->freqProcessor[i] =
+ sysInfo->freqProcessor[cpu] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
#define PME_CLK_SEL 0x80000000
#define FM1_CLK_SEL 0x40000000
#define FM2_CLK_SEL 0x20000000
+#define HWA_ASYNC_DIV 0x04000000
+#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
+#define HWA_CC_PLL 1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
+#define HWA_CC_PLL 2
+#else
+#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
+#endif
rcw_tmp = in_be32(&gur->rcwsr[7]);
#ifdef CONFIG_SYS_DPAA_PME
- if (rcw_tmp & PME_CLK_SEL)
- sysInfo->freqPME = freqCC_PLL[2] / 2;
- else
+ if (rcw_tmp & PME_CLK_SEL) {
+ if (rcw_tmp & HWA_ASYNC_DIV)
+ sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
+ else
+ sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
+ } else {
sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+ }
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
- if (rcw_tmp & FM1_CLK_SEL)
- sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
- else
+ if (rcw_tmp & FM1_CLK_SEL) {
+ if (rcw_tmp & HWA_ASYNC_DIV)
+ sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
+ else
+ sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
+ } else {
sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+ }
#if (CONFIG_SYS_NUM_FMAN) == 2
- if (rcw_tmp & FM2_CLK_SEL)
- sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
- else
+ if (rcw_tmp & FM2_CLK_SEL) {
+ if (rcw_tmp & HWA_ASYNC_DIV)
+ sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
+ else
+ sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
+ } else {
sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+ }
#endif
#endif
#else
uint plat_ratio,e500_ratio,half_freqSystemBus;
+#if defined(CONFIG_FSL_LBC)
uint lcrr_div;
+#endif
int i;
#ifdef CONFIG_QE
- u32 qe_ratio;
+ __maybe_unused u32 qe_ratio;
#endif
plat_ratio = (gur->porpllsr) & 0x0000003e;
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
#endif
-#endif
#ifdef CONFIG_QE
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ sysInfo->freqQE = sysInfo->freqSystemBus;
+#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+#endif
+
+#endif /* CONFIG_FSL_CORENET */
+#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
- {
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
- }
+ lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
/* In case anyone cares what the unknown value is */
sysInfo->freqLocalBus = lcrr_div;
}
+#endif
}
gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
-#ifdef CONFIG_MPC8569
+#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
+ defined(CONFIG_P1014)
gd->sdhc_clk = gd->bus_clk;
#else
gd->sdhc_clk = gd->bus_clk / 2;