mpc83xx: Cleanup usage of DDR constants

[u-boot] / arch / powerpc / cpu / mpc85xx / u-boot-nand_spl.lds

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 7d9cee98e51f75f10b352494d631b173bdb23d27..852f9aa4a392038212175544ecb017fca3ed2087 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -23,20 +23,22 @@
  * MA 02111-1307 USA
  */
 
+#include "config.h"    /* CONFIG_BOARDDIR */
+
 OUTPUT_ARCH(powerpc)
 SECTIONS
 {
        . = 0xfff00000;
        .text : {
-               *(.text)
+               *(.text*)
        }
        _etext = .;
 
        .reloc : {
                _GOT2_TABLE_ = .;
-               *(.got2)
+               KEEP(*(.got2))
                _FIXUP_TABLE_ = .;
-               *(.fixup)
+               KEEP(*(.fixup))
        }
        __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
        __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
@@ -52,16 +54,26 @@ SECTIONS
        . = ALIGN(8);
        __init_begin = .;
        __init_end = .;
-
-       .resetvec ADDR(.text) + 0xffc : {
-               *(.resetvec)
+#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
+       .bootpg ADDR(.text) + 0x1000 :
+       {
+               start.o (.bootpg)
+       }
+#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#elif defined(CONFIG_FSL_ELBC)
+#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
+#else
+#error unknown NAND controller
+#endif
+       .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
+               KEEP(*(.resetvec))
        } = 0xffff
 
        __bss_start = .;
        .bss : {
-               *(.sbss)
-               *(.bss)
+               *(.sbss*)
+               *(.bss*)
        }
-       _end = .;
+       __bss_end__ = .;
 }
-ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
+ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");