mpc8xx/cpu.c: Fix GCC 4.6 build warnings

[u-boot] / arch / powerpc / cpu / mpc8xx / fec.c

diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index a2d2bd6d8dd6697ed5d8c45fbc0a2f596c3650fc..f2a2c3a7369e03739e79befffe80d5d0d3f68b28 100644 (file)
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -378,35 +378,39 @@ static void fec_pin_init(int fecidx)
 {
        bd_t           *bd = gd->bd;
        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-       volatile fec_t *fecp;
-
-       /*
-        * only two FECs please
-        */
-       if ((unsigned int)fecidx >= 2)
-               hang();
-
-       if (fecidx == 0)
-               fecp = &immr->im_cpm.cp_fec1;
-       else
-               fecp = &immr->im_cpm.cp_fec2;
 
        /*
         * Set MII speed to 2.5 MHz or slightly below.
-        * * According to the MPC860T (Rev. D) Fast ethernet controller user
-        * * manual (6.2.14),
-        * * the MII management interface clock must be less than or equal
-        * * to 2.5 MHz.
-        * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
-        * * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
+        *
+        * According to the MPC860T (Rev. D) Fast ethernet controller user
+        * manual (6.2.14),
+        * the MII management interface clock must be less than or equal
+        * to 2.5 MHz.
+        * This MDC frequency is equal to system clock / (2 * MII_SPEED).
+        * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
         *
         * All MII configuration is done via FEC1 registers:
         */
        immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
 
 #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
-       /* our PHYs are the limit at 2.5 MHz */
-       fecp->fec_mii_speed <<= 1;
+       {
+               volatile fec_t *fecp;
+
+               /*
+                * only two FECs please
+                */
+               if ((unsigned int)fecidx >= 2)
+                       hang();
+
+               if (fecidx == 0)
+                       fecp = &immr->im_cpm.cp_fec1;
+               else
+                       fecp = &immr->im_cpm.cp_fec2;
+
+               /* our PHYs are the limit at 2.5 MHz */
+               fecp->fec_mii_speed <<= 1;
+       }
 #endif
 
 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
@@ -1010,11 +1014,10 @@ int fec8xx_miiphy_read(const char *devname, unsigned char addr,
 int fec8xx_miiphy_write(const char *devname, unsigned char  addr,
                unsigned char  reg, unsigned short value)
 {
-       short rdreg;    /* register working value */
 #ifdef MII_DEBUG
        printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
 #endif
-       rdreg = mii_send(mk_mii_write(addr, reg, value));
+       (void)mii_send(mk_mii_write(addr, reg, value));
 
 #ifdef MII_DEBUG
        printf ("0x%04x\n", value);