powerpc, 8xx: Add support for MCR3000 board from CSSI

[u-boot] / arch / powerpc / cpu / mpc8xx / start.S

diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index 5aa50c512c13e05d8fa2b4c2bc62e63d792a6b79..b00696fc75dcae47eef34db123b1e95344a3d91f 100644 (file)
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S
@@ -3,23 +3,7 @@
  *  Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*  U-Boot - Startup Code for PowerPC based Embedded Boards
@@ -42,9 +26,6 @@
 #include <mpc8xx.h>
 #include <version.h>
 
-#define CONFIG_8xx 1           /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1      /* avoid reading Linux autoconf.h file  */
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
@@ -125,12 +106,7 @@ _start:
        lis     r3, IDC_DISABLE@h       /* Disable data cache */
        mtspr   DC_CST, r3
 
-#if !defined(CONFIG_SYS_DELAYED_ICACHE)
-                                       /* On IP860 and PCU E,
-                                        * we cannot enable IC yet
-                                        */
        lis     r3, IDC_ENABLE@h        /* Enable instruction cache */
-#endif
        mtspr   IC_CST, r3
 
        /* invalidate all tlb's                                                 */
@@ -355,20 +331,11 @@ icache_status:
 
        .globl  dcache_enable
 dcache_enable:
-#if 0
-       SYNC
-#endif
-#if 1
        lis     r3, 0x0400              /* Set cache mode with MMU off */
        mtspr   MD_CTR, r3
-#endif
 
        lis     r3, IDC_INVALL@h
        mtspr   DC_CST, r3
-#if 0
-       lis     r3, DC_SFWT@h
-       mtspr   DC_CST, r3
-#endif
        lis     r3, IDC_ENABLE@h
        mtspr   DC_CST, r3
        blr