Merge branch 'master' of git://git.denx.de/u-boot

[u-boot] / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index c28f9cd2012496a7064134ff91e35fadc48925a3..26c42f7039033d82a8829e7b48396e6105c2daee 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -18,17 +18,9 @@
 
 #include "ddr.h"
 
-#ifdef CONFIG_MPC83xx
-       #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
-#elif defined(CONFIG_MPC85xx)
-       #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
-#elif defined(CONFIG_MPC86xx)
-       #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
-#else
-       #error "Undefined _DDR_ADDR"
-#endif
+#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
 
-u32 fsl_ddr_get_version(void)
+static u32 fsl_ddr_get_version(void)
 {
        ccsr_ddr_t *ddr;
        u32 ver_major_minor_errata;
@@ -229,6 +221,26 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 
 #if !defined(CONFIG_FSL_DDR1)
+static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
+{
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
+       if (dimm_params[0].n_ranks == 4)
+               return 1;
+#endif
+
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
+       if ((dimm_params[0].n_ranks == 2) &&
+               (dimm_params[1].n_ranks == 2))
+               return 1;
+
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+       if (dimm_params[0].n_ranks == 4)
+               return 1;
+#endif
+#endif
+       return 0;
+}
+
 /*
  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
  *
@@ -236,7 +248,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
  * dreams up non-zero default values to be backwards compatible.
  */
 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
-                               const memctl_options_t *popts)
+                               const memctl_options_t *popts,
+                               const dimm_params_t *dimm_params)
 {
        unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
        unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
@@ -266,7 +279,18 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
        unsigned int data_rate = get_ddr_freq(0);
        tmrd_mclk = 4;
        /* set the turnaround time */
-       trwt_mclk = 1;
+
+       /*
+        * for single quad-rank DIMM and two dual-rank DIMMs
+        * to avoid ODT overlap
+        */
+       if (avoid_odt_overlap(dimm_params)) {
+               twwt_mclk = 2;
+               trrt_mclk = 1;
+       }
+       /* for faster clock, need more time for data setup */
+       trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
+
        if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
                twrt_mclk = 1;
 
@@ -1166,7 +1190,11 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
 {
        unsigned int init_value;        /* Initialization value */
 
+#ifdef CONFIG_MEM_INIT_VALUE
+       init_value = CONFIG_MEM_INIT_VALUE;
+#else
        init_value = 0xDEADBEEF;
+#endif
        ddr->ddr_data_init = init_value;
 }
 
@@ -1483,7 +1511,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
                                break;
                        }
                        sa = common_dimm->base_address;
-                       ea = common_dimm->total_mem - 1;
+                       ea = sa + common_dimm->total_mem - 1;
                } else if (!popts->memctl_interleaving) {
                        /*
                         * If memory interleaving between controllers is NOT
@@ -1497,7 +1525,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
                        switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
                        case FSL_DDR_CS0_CS1_CS2_CS3:
                                sa = common_dimm->base_address;
-                               ea = common_dimm->total_mem - 1;
+                               ea = sa + common_dimm->total_mem - 1;
                                break;
                        case FSL_DDR_CS0_CS1_AND_CS2_CS3:
                                if ((i >= 2) && (dimm_number == 0)) {
@@ -1554,17 +1582,19 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
                sa >>= 24;
                ea >>= 24;
 
-               ddr->cs[i].bnds = (0
-                       | ((sa & 0xFFF) << 16)  /* starting address MSB */
-                       | ((ea & 0xFFF) << 0)   /* ending address MSB */
-                       );
+               if (cs_en) {
+                       ddr->cs[i].bnds = (0
+                               | ((sa & 0xFFF) << 16)/* starting address MSB */
+                               | ((ea & 0xFFF) << 0)   /* ending address MSB */
+                               );
+               } else {
+                       debug("FSLDDR: setting bnds to 0 for inactive CS\n");
+                       ddr->cs[i].bnds = 0;
+               }
 
                debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
-               if (cs_en) {
-                       set_csn_config(dimm_number, i, ddr, popts, dimm_params);
-                       set_csn_config_2(i, ddr);
-               } else
-                       debug("CS%d is disabled.\n", i);
+               set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+               set_csn_config_2(i, ddr);
        }
 
        /*
@@ -1577,7 +1607,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        set_ddr_eor(ddr, popts);
 
 #if !defined(CONFIG_FSL_DDR1)
-       set_timing_cfg_0(ddr, popts);
+       set_timing_cfg_0(ddr, popts, dimm_params);
 #endif
 
        set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);