Merge branch 'master' of git://git.denx.de/u-boot-sparc

[u-boot] / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index b2962d26c4caec75cc3182b35ffd21db5fc1f614..3fec100377b4ef1ed107d3b4d9ebf72a2453bc79 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -199,7 +199,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
        unsigned char act_pd_exit_mclk;
        /* Precharge powerdown exit timing (tXP). */
        unsigned char pre_pd_exit_mclk;
-       /* Precharge powerdown exit timing (tAXPD). */
+       /* ODT powerdown exit timing (tAXPD). */
        unsigned char taxpd_mclk;
        /* Mode register set cycle time (tMRD). */
        unsigned char tmrd_mclk;
@@ -211,13 +211,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
         * we use the tXP instead of it.
         * tXP=max(3nCK, 7.5ns) for DDR3.
         * spec has not the tAXPD, we use
-        * tAXPD=8, need design to confirm.
+        * tAXPD=1, need design to confirm.
         */
        int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
        act_pd_exit_mclk = picos_to_mclk(tXP);
        /* Mode register MR0[A12] is '1' - fast exit */
        pre_pd_exit_mclk = act_pd_exit_mclk;
-       taxpd_mclk = 8;
+       taxpd_mclk = 1;
        tmrd_mclk = 4;
        /* set the turnaround time */
        trwt_mclk = 1;
@@ -613,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR3)
        md_en = popts->mirrored_dimm;
 #endif
+       rcw_en = popts->registered_dimm_en;
        qd_en = popts->quad_rank_present ? 1 : 0;
        ddr->ddr_sdram_cfg_2 = (0
                | ((frc_sr & 0x1) << 31)
@@ -1031,9 +1032,9 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
        unsigned int wodt_off = 0;      /* Write to ODT off */
 
 #if defined(CONFIG_FSL_DDR3)
-       rodt_on = 3;    /*  2 clocks */
+       rodt_on = 2;    /*  2 clocks */
        rodt_off = 4;   /*  4 clocks */
-       wodt_on = 2;    /*  1 clocks */
+       wodt_on = 1;    /*  1 clocks */
        wodt_off = 4;   /*  4 clocks */
 #endif
 
@@ -1106,9 +1107,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
                /*
                 * Write leveling repetition time
                 * at least tWLO + 6 clocks clocks
-                * we set it 32
+                * we set it 64
                 */
-               wrlvl_wlr = 0x5;
+               wrlvl_wlr = 0x6;
                /*
                 * Write leveling start time
                 * The value use for the DQS_ADJUST for the first sample
@@ -1183,6 +1184,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        unsigned int sr_it;
        unsigned int zq_en;
        unsigned int wrlvl_en;
+       int cs_en = 1;
 
        memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
 
@@ -1249,16 +1251,23 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
                         * and each controller uses rank interleaving within
                         * itself. Therefore the starting and ending address
                         * on each controller is twice the amount present on
-                        * each controller.
+                        * each controller. If any CS is not included in the
+                        * interleaving, the memory on that CS is not accssible
+                        * and the total memory size is reduced. The CS is also
+                        * disabled.
                         */
                        unsigned long long ctlr_density = 0;
                        switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
                        case FSL_DDR_CS0_CS1:
                        case FSL_DDR_CS0_CS1_AND_CS2_CS3:
                                ctlr_density = dimm_params[0].rank_density * 2;
+                               if (i > 1)
+                                       cs_en = 0;
                                break;
                        case FSL_DDR_CS2_CS3:
                                ctlr_density = dimm_params[0].rank_density;
+                               if (i > 0)
+                                       cs_en = 0;
                                break;
                        case FSL_DDR_CS0_CS1_CS2_CS3:
                                /*
@@ -1378,8 +1387,11 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
                        );
 
                debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
-               set_csn_config(dimm_number, i, ddr, popts, dimm_params);
-               set_csn_config_2(i, ddr);
+               if (cs_en) {
+                       set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+                       set_csn_config_2(i, ddr);
+               } else
+                       printf("CS%d is disabled.\n", i);
        }
 
        set_ddr_eor(ddr, popts);