Merge branch 'u-boot/master' into u-boot-arm/master

[u-boot] / arch / powerpc / cpu / mpc8xxx / srio.c

diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e7ff59a1ca963aa06eb8574630135ee649f7e024..0ab9aac4a88d2e21c7bd77c3d5eb07334695fcc7 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -1,20 +1,7 @@
 /*
  * Copyright 2011 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -24,6 +11,7 @@
 #include <asm/fsl_srio.h>
 #include <asm/errno.h>
 
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 #define SRIO_PORT_ACCEPT_ALL 0x10000001
 #define SRIO_IB_ATMU_AR 0x80f55000
 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -32,10 +20,16 @@
 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
 #define SRIO_LCSBA1CSR 0x60000000
+#endif
 
 #if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
+       #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
+#else
        #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
        #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+#endif
        #define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
        #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
@@ -236,7 +230,13 @@ void srio_init(void)
 {
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
        int srio1_used = 0, srio2_used = 0;
+       u32 *devdisr;
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       devdisr = &gur->devdisr3;
+#else
+       devdisr = &gur->devdisr;
+#endif
        if (is_serdes_configured(SRIO1)) {
                set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
                                law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
@@ -273,20 +273,20 @@ void srio_init(void)
 #ifdef CONFIG_FSL_CORENET
        /* On FSL_CORENET devices we can disable individual ports */
        if (!srio1_used)
-               setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+               setbits_be32(devdisr, _DEVDISR_SRIO1);
        if (!srio2_used)
-               setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+               setbits_be32(devdisr, _DEVDISR_SRIO2);
 #endif
 
        /* neither port is used - disable everything */
        if (!srio1_used && !srio2_used) {
-               setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
-               setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
-               setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+               setbits_be32(devdisr, _DEVDISR_SRIO1);
+               setbits_be32(devdisr, _DEVDISR_SRIO2);
+               setbits_be32(devdisr, _DEVDISR_RMU);
        }
 }
 
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
        struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;