serial: drop useless ctlr field

[u-boot] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr2.c

diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index faddee98b781df101c16d1614ec713d003e6d12b..95df1d94c4713c8878eb3a8f504da665a6dfc2c4 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -41,7 +41,7 @@
 
 #include <common.h>
 #include <command.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/processor.h>
@@ -50,8 +50,6 @@
 
 #include "ecc.h"
 
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-
 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                                \
        do {                                                            \
                u32 data;                                               \
@@ -68,6 +66,31 @@
                       "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
        } while (0)
 
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+static void update_rdcc(void)
+{
+       u32 val;
+
+       /*
+        * Complete RDSS configuration as mentioned on page 7 of the AMCC
+        * PowerPC440SP/SPe DDR2 application note:
+        * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+        *
+        * Or item #10 "10. Complete RDSS configuration" in chapter
+        * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
+        * manual.
+        */
+       mfsdram(SDRAM_RTSR, val);
+       if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
+               mfsdram(SDRAM_RDCC, val);
+               if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
+                       val += 0x40000000;
+                       mtsdram(SDRAM_RDCC, val);
+               }
+       }
+}
+#endif
+
 #if defined(CONFIG_440)
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
@@ -393,7 +416,6 @@ static void test(void);
 static void    DQS_calibration_process(void);
 #endif
 #endif
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 static unsigned char spd_read(uchar chip, uint addr)
 {
@@ -444,7 +466,7 @@ phys_size_t initdram(int board_type)
        /*------------------------------------------------------------------
         * Reset the DDR-SDRAM controller.
         *-----------------------------------------------------------------*/
-       mtsdr(SDR0_SRST, (0x80000000 >> 10));
+       mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
        mtsdr(SDR0_SRST, 0x00000000);
 
        /*
@@ -620,6 +642,12 @@ phys_size_t initdram(int board_type)
 #else
        program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 #endif
+       /*
+        * Now complete RDSS configuration as mentioned on page 7 of the AMCC
+        * PowerPC440SP/SPe DDR2 application note:
+        * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+        */
+       update_rdcc();
 
 #ifdef CONFIG_DDR_ECC
        /*------------------------------------------------------------------
@@ -2692,20 +2720,6 @@ calibration_loop:
        blank_string(strlen(str));
 #endif /* CONFIG_DDR_RQDC_FIXED */
 
-       /*
-        * Now complete RDSS configuration as mentioned on page 7 of the AMCC
-        * PowerPC440SP/SPe DDR2 application note:
-        * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
-        */
-       mfsdram(SDRAM_RTSR, val);
-       if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
-               mfsdram(SDRAM_RDCC, val);
-               if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
-                       val += 0x40000000;
-                       mtsdram(SDRAM_RDCC, val);
-               }
-       }
-
        mfsdram(SDRAM_DLCR, val);
        debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
        mfsdram(SDRAM_RQDC, val);
@@ -3007,6 +3021,13 @@ phys_size_t initdram(int board_type)
 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
+       /*
+        * Now complete RDSS configuration as mentioned on page 7 of the AMCC
+        * PowerPC440SP/SPe DDR2 application note:
+        * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+        */
+       update_rdcc();
+
 #if defined(CONFIG_DDR_ECC)
        do_program_ecc(0);
 #endif /* defined(CONFIG_DDR_ECC) */
@@ -3170,5 +3191,3 @@ inline void ppc4xx_ibm_ddr2_register_dump(void)
        PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
 #endif /* defined(DEBUG) */
 }
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */