Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze

[u-boot] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 712f2ef4b3020aab86eefd459b0d9e324e068924..01b09058cc3fb8765622e17379765f6d71031435 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -24,6 +24,7 @@
 
 /* IP endianness */
 #define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SEC_BE
 
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
@@ -677,6 +678,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007798
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -767,6 +769,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
+#define CONFIG_SYS_FSL_ERRATUM_A008044
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
@@ -784,6 +787,52 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
 
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
+defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET          /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3  /* QMAN version 3 */
+#define CONFIG_SYS_FMAN_V3
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#endif
+#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#define CONFIG_MAX_CPUS                        2
+#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define CONFIG_MAX_CPUS                        1
+#endif
+#define CONFIG_SYS_FSL_NUM_CC_PLL      2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
+#define CONFIG_SYS_SDHC_CLOCK          0
+#define CONFIG_SYS_FSL_NUM_LAWS                16
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SEC_COMPAT      5
+#define CONFIG_SYS_NUM_FMAN            1
+#define CONFIG_SYS_NUM_FM1_DTSEC       4
+#define CONFIG_SYS_NUM_FM1_10GEC       1
+#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#define CONFIG_SYS_FSL_DDR_VER  FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
+#define CONFIG_SYS_FM1_CLK             0
+#define CONFIG_QBMAN_CLK_DIV           1
+#define CONFIG_SYS_FM_MURAM_SIZE       0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV       16
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE                  0x6000UL
+#define MAX_QE_RISC                    1
+#define QE_NUM_OF_SNUM                 28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64               /* 64-bit core */