]> git.sur5r.net Git - u-boot/blobdiff - arch/powerpc/include/asm/config_mpc85xx.h
Merge remote-tracking branch 'u-boot/master'
[u-boot] / arch / powerpc / include / asm / config_mpc85xx.h
index fe68e0e28086a2c5ad3a4ca26052dba05552921c..34fc8fb5347f3a47217f414b50dbbb6b49710f0a 100644 (file)
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
 #define CONFIG_ESDHC_HC_BLK_ADDR
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#endif
 
 #elif defined(CONFIG_P1021)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A005434
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_NUM_FM2_10GEC       2
 #define CONFIG_NUM_DDR_CONTROLLERS     3
 #else
-#define CONFIG_MAX_CPUS                        8
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1 }
-#define CONFIG_SYS_NUM_FM1_DTSEC       7
+#define CONFIG_SYS_NUM_FM1_DTSEC       6
 #define CONFIG_SYS_NUM_FM1_10GEC       1
-#define CONFIG_SYS_NUM_FM2_DTSEC       7
+#define CONFIG_SYS_NUM_FM2_DTSEC       8
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     2
+#if defined(CONFIG_PPC_T4160)
+#define CONFIG_MAX_CPUS                        8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1 }
+#elif defined(CONFIG_PPC_T4080)
+#define CONFIG_MAX_CPUS                        4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1 }
+#endif
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     5
 #define CONFIG_SYS_FSL_NUM_LAWS                32
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006475
 #define CONFIG_SYS_FSL_ERRATUM_A006384
+#define CONFIG_SYS_FSL_ERRATUM_A007212
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
 #ifdef CONFIG_PPC_B4860
@@ -789,10 +802,14 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v3.0"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A007212
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER                2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006379
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE