Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / arch / powerpc / include / asm / fsl_ddr_dimm_params.h

diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index 55923e09b3a315d25beb2b491b96589c0dcac984..bd312ad5c58c20f0233d007f9b98c8dd2bf5333b 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -9,6 +9,10 @@
 #ifndef DDR2_DIMM_PARAMS_H
 #define DDR2_DIMM_PARAMS_H
 
+#define EDC_DATA_PARITY        1
+#define EDC_ECC                2
+#define EDC_AC_PARITY  4
+
 /* Parameters for a DDR2 dimm computed from the SPD */
 typedef struct dimm_params_s {
 
@@ -22,6 +26,7 @@ typedef struct dimm_params_s {
        unsigned int primary_sdram_width;
        unsigned int ec_sdram_width;
        unsigned int registered_dimm;
+       unsigned int device_width;      /* x4, x8, x16 components */
 
        /* SDRAM device parameters */
        unsigned int n_row_addr;
@@ -39,6 +44,7 @@ typedef struct dimm_params_s {
        /* DIMM timing parameters */
 
        unsigned int mtb_ps;    /* medium timebase ps, only for ddr3 */
+       unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
        unsigned int tAA_ps;    /* minimum CAS latency time, only for ddr3 */
        unsigned int tFAW_ps;   /* four active window delay, only for ddr3 */
 
@@ -81,6 +87,9 @@ typedef struct dimm_params_s {
        unsigned int tRTP_ps;   /* byte 38, spd->trtp */
        unsigned int tDQSQ_max_ps;      /* byte 44, spd->tdqsq */
        unsigned int tQHS_ps;   /* byte 45, spd->tqhs */
+
+       /* DDR3 RDIMM */
+       unsigned char rcw[16];  /* Register Control Word 0-15 */
 } dimm_params_t;
 
 extern unsigned int ddr_compute_dimm_parameters(