Merge branch 'master' of git://git.denx.de/u-boot-spi

[u-boot] / arch / powerpc / include / asm / fsl_ddr_sdram.h

diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 02a1f5d32339f15058f8b5027f271e3c3b409e88..640d3297d6c89a36725eacd1413911e045d1456c 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -31,6 +31,11 @@
 #define DDR3_RTT_20_OHM                4 /* RTT_Nom = RZQ/12 */
 #define DDR3_RTT_30_OHM                5 /* RTT_Nom = RZQ/8 */
 
+#define DDR2_RTT_OFF           0
+#define DDR2_RTT_75_OHM                1
+#define DDR2_RTT_150_OHM       2
+#define DDR2_RTT_50_OHM                3
+
 #if defined(CONFIG_FSL_DDR1)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR       (1)
 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
@@ -71,6 +76,15 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define FSL_DDR_PAGE_INTERLEAVING      0x1
 #define FSL_DDR_BANK_INTERLEAVING      0x2
 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+#define FSL_DDR_3WAY_1KB_INTERLEAVING  0xA
+#define FSL_DDR_3WAY_4KB_INTERLEAVING  0xC
+#define FSL_DDR_3WAY_8KB_INTERLEAVING  0xD
+/* placeholder for 4-way interleaving */
+#define FSL_DDR_4WAY_1KB_INTERLEAVING  0x1A
+#define FSL_DDR_4WAY_4KB_INTERLEAVING  0x1C
+#define FSL_DDR_4WAY_8KB_INTERLEAVING  0x1D
+
+#define SDRAM_CS_CONFIG_EN             0x80000000
 
 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  */
@@ -83,7 +97,10 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_SDRAM_TYPE_MASK      0x07000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT     24
 #define SDRAM_CFG_DYN_PWR              0x00200000
+#define SDRAM_CFG_DBW_MASK             0x00180000
+#define SDRAM_CFG_DBW_SHIFT            19
 #define SDRAM_CFG_32_BE                        0x00080000
+#define SDRAM_CFG_16_BE                        0x00100000
 #define SDRAM_CFG_8_BE                 0x00040000
 #define SDRAM_CFG_NCAP                 0x00020000
 #define SDRAM_CFG_2T_EN                        0x00008000
@@ -91,6 +108,10 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 
 #define SDRAM_CFG2_D_INIT              0x00000010
 #define SDRAM_CFG2_ODT_CFG_MASK                0x00600000
+#define SDRAM_CFG2_ODT_NEVER           0
+#define SDRAM_CFG2_ODT_ONLY_WRITE      1
+#define SDRAM_CFG2_ODT_ONLY_READ       2
+#define SDRAM_CFG2_ODT_ALWAYS          3
 
 #define TIMING_CFG_2_CPO_MASK  0x0F800000
 
@@ -127,6 +148,31 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 
 /* DDR_CDR1 */
 #define DDR_CDR1_DHC_EN        0x80000000
+#define DDR_CDR1_ODT_SHIFT     17
+#define DDR_CDR1_ODT_MASK      0x6
+#define DDR_CDR2_ODT_MASK      0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+       (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#define DDR_CDR_ODT_OFF                0x0
+#define DDR_CDR_ODT_120ohm     0x1
+#define DDR_CDR_ODT_180ohm     0x2
+#define DDR_CDR_ODT_75ohm      0x3
+#define DDR_CDR_ODT_110ohm     0x4
+#define DDR_CDR_ODT_60hm       0x5
+#define DDR_CDR_ODT_70ohm      0x6
+#define DDR_CDR_ODT_47ohm      0x7
+#else
+#define DDR_CDR_ODT_75ohm      0x0
+#define DDR_CDR_ODT_55ohm      0x1
+#define DDR_CDR_ODT_60ohm      0x2
+#define DDR_CDR_ODT_50ohm      0x3
+#define DDR_CDR_ODT_150ohm     0x4
+#define DDR_CDR_ODT_43ohm      0x5
+#define DDR_CDR_ODT_120ohm     0x6
+#endif
 
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
@@ -159,6 +205,8 @@ typedef struct fsl_ddr_cfg_regs_s {
        unsigned int timing_cfg_5;
        unsigned int ddr_zq_cntl;
        unsigned int ddr_wrlvl_cntl;
+       unsigned int ddr_wrlvl_cntl_2;
+       unsigned int ddr_wrlvl_cntl_3;
        unsigned int ddr_sr_cntr;
        unsigned int ddr_sdram_rcw_1;
        unsigned int ddr_sdram_rcw_2;
@@ -180,6 +228,9 @@ typedef struct memctl_options_partial_s {
        unsigned int all_DIMMs_minimum_tRCD_ps;
 } memctl_options_partial_t;
 
+#define DDR_DATA_BUS_WIDTH_64 0
+#define DDR_DATA_BUS_WIDTH_32 1
+#define DDR_DATA_BUS_WIDTH_16 2
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller
@@ -241,6 +292,8 @@ typedef struct memctl_options_s {
        unsigned int wrlvl_override;
        unsigned int wrlvl_sample;              /* Write leveling */
        unsigned int wrlvl_start;
+       unsigned int wrlvl_ctl_2;
+       unsigned int wrlvl_ctl_3;
 
        unsigned int half_strength_driver_enable;
        unsigned int twoT_en;
@@ -267,10 +320,18 @@ typedef struct memctl_options_s {
        unsigned int rcw_2;
        /* control register 1 */
        unsigned int ddr_cdr1;
+       unsigned int ddr_cdr2;
+
+       unsigned int trwt_override;
+       unsigned int trwt;                      /* read-to-write turnaround */
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);
+extern phys_size_t fsl_ddr_sdram_size(void);
 extern int fsl_use_spd(void);
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+                                       unsigned int ctrl_num);
+u32 fsl_ddr_get_intl3r(void);
 
 /*
  * The 85xx boards have a common prototype for fixed_sdram so put the