powerpc/mp: add support for discontiguous cores

[u-boot] / arch / powerpc / include / asm / fsl_ddr_sdram.h

diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index b5b1efe66925cbfd249aad32689d6c22091b84a2..bc063ea892ae0447f7adf8e33bfaaf731dbc9f1b 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -84,6 +84,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT     24
 #define SDRAM_CFG_DYN_PWR              0x00200000
 #define SDRAM_CFG_32_BE                        0x00080000
+#define SDRAM_CFG_16_BE                        0x00100000
 #define SDRAM_CFG_8_BE                 0x00040000
 #define SDRAM_CFG_NCAP                 0x00020000
 #define SDRAM_CFG_2T_EN                        0x00008000
@@ -180,6 +181,9 @@ typedef struct memctl_options_partial_s {
        unsigned int all_DIMMs_minimum_tRCD_ps;
 } memctl_options_partial_t;
 
+#define DDR_DATA_BUS_WIDTH_64 0
+#define DDR_DATA_BUS_WIDTH_32 1
+#define DDR_DATA_BUS_WIDTH_16 2
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller
@@ -267,9 +271,13 @@ typedef struct memctl_options_s {
        unsigned int rcw_2;
        /* control register 1 */
        unsigned int ddr_cdr1;
+
+       unsigned int trwt_override;
+       unsigned int trwt;                      /* read-to-write turnaround */
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);
+extern phys_size_t fsl_ddr_sdram_size(void);
 extern int fsl_use_spd(void);
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                                        unsigned int ctrl_num);