Merge branch 'master' of git://git.denx.de/u-boot-spi

[u-boot] / arch / powerpc / include / asm / fsl_ifc.h

diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index d4d98090556a90738fc04c884d591107a033b292..ba41b73cc0389b149e4c13fdc1d176a31088a9c1 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -69,6 +69,7 @@
  */
 /* Enable ECC Encoder */
 #define CSOR_NAND_ECC_ENC_EN           0x80000000
+#define CSOR_NAND_ECC_MODE_MASK                0x30000000
 /* 4 bit correction per 520 Byte sector */
 #define CSOR_NAND_ECC_MODE_4           0x00000000
 /* 8 bit correction per 528 Byte sector */
@@ -782,12 +783,16 @@ extern void init_early_memctl_regs(void);
 
 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
 
+#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
 #define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
 #define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
 #define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
 #define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
 
+#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
 #define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
 #define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
 #define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
 #define set_ifc_ftim(i, j, v) \
@@ -857,10 +862,7 @@ struct fsl_ifc_nand {
        u32 res19[0x10];
        u32 nand_fsr;
        u32 res20;
-       u32 nand_eccstat0;
-       u32 nand_eccstat1;
-       u32 nand_eccstat2;
-       u32 nand_eccstat3;
+       u32 nand_eccstat[4];
        u32 res21[0x20];
        u32 nanndcr;
        u32 res22[0x2];
@@ -911,22 +913,24 @@ struct fsl_ifc_gpcm {
  */
 struct fsl_ifc {
        u32 ifc_rev;
-       u32 res1[0x3];
+       u32 res1[0x2];
        struct {
+               u32 cspr_ext;
                u32 cspr;
-               u32 res2[0x2];
+               u32 res2;
        } cspr_cs[FSL_IFC_BANK_COUNT];
-       u32 res3[0x18];
+       u32 res3[0x19];
        struct {
                u32 amask;
                u32 res4[0x2];
        } amask_cs[FSL_IFC_BANK_COUNT];
-       u32 res5[0x18];
+       u32 res5[0x17];
        struct {
+               u32 csor_ext;
                u32 csor;
-               u32 res6[0x2];
+               u32 res6;
        } csor_cs[FSL_IFC_BANK_COUNT];
-       u32 res7[0x18];
+       u32 res7[0x19];
        struct {
                u32 ftim[4];
                u32 res8[0x8];
@@ -953,5 +957,10 @@ struct fsl_ifc {
        struct fsl_ifc_gpcm ifc_gpcm;
 };
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR  CSPR_MSEL_GPCM
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */