/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#define __FSL_PCI_H_
#include <asm/fsl_law.h>
-
-int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel);
+#include <asm/fsl_serdes.h>
+#include <pci.h>
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
-void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
-void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
/*
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
} ccsr_fsl_pci_t;
struct fsl_pci_info {
- unsigned long regs;
- pci_addr_t mem_bus;
- phys_size_t mem_phys;
- pci_size_t mem_size;
- pci_addr_t io_bus;
- phys_size_t io_phys;
- pci_size_t io_size;
- int pci_num;
+ unsigned long regs;
+ pci_addr_t mem_bus;
+ phys_size_t mem_phys;
+ pci_size_t mem_size;
+ pci_addr_t io_bus;
+ phys_size_t io_phys;
+ pci_size_t io_size;
+ enum law_trgt_if law;
+ int pci_num;
};
+void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+ struct fsl_pci_info *pci_info);
+int fsl_pcie_init_board(int busno);
#define SET_STD_PCI_INFO(x, num) \
{ \
x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCI_##num; \
x.pci_num = num; \
}
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCIE_##num; \
x.pci_num = num; \
}
+#define __FT_FSL_PCI_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
+
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
+
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
+
+#if defined(CONFIG_FSL_CORENET)
+#define FSL_PCIE_COMPAT "fsl,p4080-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP; \
+ FT_FSL_PCIE4_SETUP;
+#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
+#elif defined(CONFIG_MPC85xx)
+#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
+#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCI2_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP;
+#define FT_FSL_PCIE_SETUP \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP;
+#elif defined(CONFIG_MPC86xx)
+#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
+#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP;
+#else
+#error FT_FSL_PCI_SETUP not defined
+#endif
+
+
#endif