/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
*
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_PCI_H_
#define __FSL_PCI_H_
#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <pci.h>
+
+#define PEX_IP_BLK_REV_2_2 0x02080202
+#define PEX_IP_BLK_REV_2_3 0x02080203
+#define PEX_IP_BLK_REV_3_0 0x02080300
-int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel);
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR 0x44
+
+#define FSL_PCIE_CFG_RDY 0x4b0
+#define FSL_PCIE_V3_CFG_RDY 0x1
+#define FSL_PROG_IF_AGENT 0x1
+
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
-void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
-void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
/*
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
u32 config; /* 0x014 - PCIE CONFIG Register */
- char res2[8];
+ u32 int_status; /* 0x018 - PCIE interrupt status register */
+ char res2[4];
u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
u32 pm_command; /* 0x02c - PCIE PM Command register */
- char res4[3016]; /* (- #xbf8 #x30)3016 */
+ char res3[2188]; /* (0x8bc - 0x30 = 2188) */
+ u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */
+ char res4[824]; /* (0xbf8 - 0x8c0 = 824) */
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
- u32 res5[64];
- pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
+ u32 res5[24];
+ pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */
+ u32 res6[24];
+ pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
+
#define PIT3 0
#define PIT2 1
#define PIT1 2
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
char res23[200];
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
- char res24[252];
+ char res24[16];
+ u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/
+ u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/
+ char res25[228];
} ccsr_fsl_pci_t;
+#define PCIE_CONFIG_PC 0x00020000
+#define PCIE_CONFIG_OB_CK 0x00002000
+#define PCIE_CONFIG_SAC 0x00000010
+#define PCIE_CONFIG_SP 0x80000002
+#define PCIE_CONFIG_SCC 0x80000001
struct fsl_pci_info {
unsigned long regs;
int pci_num;
};
+void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+ struct fsl_pci_info *pci_info);
+int fsl_pcie_init_board(int busno);
#define SET_STD_PCI_INFO(x, num) \
{ \
x.pci_num = num; \
}
+#define __FT_FSL_PCI_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
+
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
+
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
+
+#if !defined(CONFIG_PCI)
+#define FT_FSL_PCI_SETUP
+#elif defined(CONFIG_FSL_CORENET)
+#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP; \
+ FT_FSL_PCIE4_SETUP;
+#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
+#elif defined(CONFIG_MPC85xx)
+#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
+#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
+#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
+#else
+#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
+#endif
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCI2_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP;
+#define FT_FSL_PCIE_SETUP \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP;
+#elif defined(CONFIG_MPC86xx)
+#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
+#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP;
+#else
+#error FT_FSL_PCI_SETUP not defined
+#endif
+
+
#endif
projects / u-boot / blobdiff