Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / arch / powerpc / include / asm / immap_512x.h

diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 8bce586b53815a3b52cba71e9d8d5dbb8feab2f2..6086a73ba95598cc3b35f2ecf00aa60c7268160d 100644 (file)
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -3,20 +3,7 @@
  *
  * MPC512x Internal Memory Map
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  *
  * Based on the MPC83xx header.
  */
@@ -72,7 +59,6 @@ typedef struct sysconf512x {
        u8 res2[0x28];
        law512x_t ddrlaw;       /* DDR Local Access Window */
        u8 res3[0x18];
-       u32 mbxbar;             /* MBX Base Address */
        u32 srambar;            /* SRAM Base Address */
        u32 nfcbar;             /* NFC Base Address */
        u8 res4[0x34];
@@ -227,7 +213,9 @@ typedef struct clk512x {
 #define CLOCK_SCCR2_IIM_EN             0x00080000
 
 /* SCFR1 System Clock Frequency Register 1 */
+#ifndef SCFR1_IPS_DIV
 #define SCFR1_IPS_DIV          0x3
+#endif
 #define SCFR1_IPS_DIV_MASK     0x03800000
 #define SCFR1_IPS_DIV_SHIFT    23
 
@@ -238,6 +226,12 @@ typedef struct clk512x {
 #define SCFR1_LPC_DIV_MASK     0x00003800
 #define SCFR1_LPC_DIV_SHIFT    11
 
+#define SCFR1_NFC_DIV_MASK     0x00000700
+#define SCFR1_NFC_DIV_SHIFT    8
+
+#define SCFR1_DIU_DIV_MASK     0x000000FF
+#define SCFR1_DIU_DIV_SHIFT    0
+
 /* SCFR2 System Clock Frequency Register 2 */
 #define SCFR2_SYS_DIV          0xFC000000
 #define SCFR2_SYS_DIV_SHIFT    26
@@ -284,8 +278,8 @@ typedef struct ddr512x {
        u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
        u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
        u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
-       u32 DQS_config_offset_count;    /* DQS Config Offset Count */
-       u32 DQS_config_offset_time;     /* DQS Config Offset Time */
+       u32 dqs_config_offset_count;    /* DQS Config Offset Count */
+       u32 dqs_config_offset_time;     /* DQS Config Offset Time */
        u32 DQS_delay_status;   /* DQS Delay Status */
        u32 res0[0xF];
        u32 prioman_config1;    /* Priority Manager Configuration */
@@ -343,6 +337,7 @@ typedef struct ddr512x {
 
 /* MDDRC SYS CFG and Timing CFG0 Registers */
 #define MDDRC_SYS_CFG_EN       0xF0000000
+#define MDDRC_SYS_CFG_CKE_MASK 0x40000000
 #define MDDRC_SYS_CFG_CMD_MASK 0x10000000
 #define MDDRC_REFRESH_ZERO_MASK        0x0000FFFF
 
@@ -356,6 +351,11 @@ typedef struct ddr512x_config {
        u32 ddr_time_config2;   /* Timing Configuration Register */
 } ddr512x_config_t;
 
+typedef struct sdram_conf_s {
+       unsigned long size;
+       ddr512x_config_t cfg;
+} sdram_conf_t;
+
 /*
  * DMA/Messaging Unit
  */
@@ -848,10 +848,6 @@ typedef struct ioctrl512x {
        u8      reserved[0x0cfc];               /* fill to 4096 bytes size */
 } ioctrl512x_t;
 
-/* Indexes in regs array */
-/* Set for DDR */
-#define IOCTRL_MUX_DDR         0x00000036
-
 /* IO pin fields */
 #define IO_PIN_FMUX(v) ((v) << 7)      /* pin function */
 #define IO_PIN_HOLD(v) ((v) << 5)      /* hold time, pci only */
@@ -869,6 +865,19 @@ typedef struct iopin_t {
 
 void iopin_initialize(iopin_t *,int);
 
+/*
+ * support to adjust individual parts of the IO pin setup
+ */
+
+#define IO_PIN_OVER_EACH       (1 << 0) /* for compatibility */
+#define IO_PIN_OVER_FMUX       (1 << 1)
+#define IO_PIN_OVER_HOLD       (1 << 2)
+#define IO_PIN_OVER_PULL       (1 << 3)
+#define IO_PIN_OVER_STRIG      (1 << 4)
+#define IO_PIN_OVER_DRVSTR     (1 << 5)
+
+void iopin_initialize_bits(iopin_t *, int);
+
 /*
  * IIM
  */
@@ -1245,4 +1254,10 @@ static inline u32 get_pata_base (void)
 }
 #endif /* __ASSEMBLY__ */
 
+#define CONFIG_SYS_MPC512x_USB1_OFFSET   0x4000
+#define CONFIG_SYS_MPC512x_USB1_ADDR \
+                       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
+
+#define IIM_BASE_ADDR  (CONFIG_SYS_IMMR + offsetof(immap_t, iim))
+
 #endif /* __IMMAP_512x__ */