powerpc/usb:Differentiate USB controller base address

[u-boot] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index db9f22025e9431a2d13991de1a7e6ae03932f669..060e0d769be81176ac45d431da1049cf81f339c6 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1671,6 +1671,7 @@ typedef struct cpc_corenet {
 #define CPC_HDBCR0_CDQ_SPEC_DIS        0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS   0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS  0x00400000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN      0x003c0000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
@@ -2016,20 +2017,13 @@ typedef struct ccsr_clk {
                u8  res_004[0x0c];
                u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
                u8  res_014[0x0c];
-       } clkcsr[8];
-       u8      res_100[0x700]; /* 0x100 */
-       u32     pllc1gsr;       /* 0x800 Cluster PLL 1 General Status */
-       u8      res10[0x1c];
-       u32     pllc2gsr;       /* 0x820 Cluster PLL 2 General Status */
-       u8      res11[0x1c];
-       u32     pllc3gsr;       /* 0x840 Cluster PLL 3 General Status */
-       u8      res12[0x1c];
-       u32     pllc4gsr;       /* 0x860 Cluster PLL 4 General Status */
-       u8      res13[0x1c];
-       u32     pllc5gsr;       /* 0x880 Cluster PLL 5 General Status */
-       u8      res14[0x1c];
-       u32     pllc6gsr;       /* 0x8a0 Cluster PLL 6 General Status */
-       u8      res15[0x35c];
+       } clkcsr[12];
+       u8      res_100[0x680]; /* 0x100 */
+       struct {
+               u32 pllcngsr;
+               u8 res10[0x1c];
+       } pllcgsr[12];
+       u8      res21[0x280];
        u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
        u8      res16[0x1c];
        u32     plldgsr;        /* 0xc20 DDR PLL General Status */
@@ -2147,6 +2141,11 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT       25
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORPLLSR_DDR_RATIO     0x00003f00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT       (9 - ((gur->pordevsr2 \
+                                       & MPC85xx_PORDEVSR2_DDR_SPD_0) \
+                                       >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x00003f00
@@ -2194,6 +2193,9 @@ typedef struct ccsr_gur {
 #elif defined(CONFIG_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL                0x00FE0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  17
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR_IO_SEL                0x00e00000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
 #else
 #define MPC85xx_PORDEVSR_IO_SEL                0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  19
@@ -2209,6 +2211,10 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID    0x00000007
        u32     pordbgmsr;      /* POR debug mode status */
        u32     pordevsr2;      /* POR I/O device status 2 */
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR2_DDR_SPD_0    0x00000008
+#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT      3
+#endif
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG      0x00000080
        u8      res1[8];
@@ -2354,6 +2360,11 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_BSC9132
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK   0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL                0x00014000
+#endif
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PMUXCR_SPI_MASK                        0x00000300
+#define MPC85xx_PMUXCR_SPI                     0x00000000
+#define MPC85xx_PMUXCR_SPI_GPIO                        0x00000100
 #endif
        u32     pmuxcr2;        /* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
@@ -2829,54 +2840,6 @@ typedef struct ccsr_pme {
        u8      res4[0x400];
 } ccsr_pme_t;
 
-#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-struct ccsr_usb_port_ctrl {
-       u32     ctrl;
-       u32     drvvbuscfg;
-       u32     pwrfltcfg;
-       u32     sts;
-       u8      res_14[0xc];
-       u32     bistcfg;
-       u32     biststs;
-       u32     abistcfg;
-       u32     abiststs;
-       u8      res_30[0x10];
-       u32     xcvrprg;
-       u32     anaprg;
-       u32     anadrv;
-       u32     anasts;
-};
-
-typedef struct ccsr_usb_phy {
-       u32     id;
-       struct  ccsr_usb_port_ctrl port1;
-       u8      res_50[0xc];
-       u32     tvr;
-       u32     pllprg[4];
-       u8      res_70[0x4];
-       u32     anaccfg;
-       u32     dbg;
-       u8      res_7c[0x4];
-       struct  ccsr_usb_port_ctrl port2;
-       u8      res_dc[0x334];
-} ccsr_usb_phy_t;
-
-#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
-#else
-typedef struct ccsr_usb_phy {
-       u8      res0[0x18];
-       u32     usb_enable_override;
-       u8      res[0xe4];
-} ccsr_usb_phy_t;
-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
-#endif
-
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
        u8      res0[0x543];
@@ -2969,7 +2932,6 @@ struct ccsr_pman {
 #endif
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x211000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET          CONFIG_SYS_MPC85xx_USB1_OFFSET
 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET                0x220000
@@ -3022,16 +2984,22 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x1e000
 #define CONFIG_SYS_MPC85xx_L2_OFFSET           0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET          0x21000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET          0x22000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x22000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET                        0xB0000
+#elif defined(CONFIG_TSECV2_1)
+#define CONFIG_SYS_TSEC1_OFFSET                        0x10000
 #else
 #define CONFIG_SYS_TSEC1_OFFSET                        0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET                        0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x2e000
+#if defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_SEC_OFFSET              0x80000
+#else
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x30000
+#endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
 #define CONFIG_SYS_SNVS_OFFSET                 0xE6000
@@ -3117,8 +3085,10 @@ struct ccsr_pman {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \