Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0264523d6402779e094ed5fee993f9fddcc95be0..101b8db0ee455d97593c9fc8b51edeb3bfa9a0f3 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -17,8 +17,9 @@
 #include <asm/fsl_i2c.h>
 #include <fsl_ifc.h>
 #include <fsl_sec.h>
+#include <fsl_sfp.h>
 #include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 #include <fsl_immap.h>
 
 typedef struct ccsr_local {
@@ -1626,10 +1627,15 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC1_6  0x04000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_9  0x00800000
 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
+#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define FSL_CORENET_DEVDISR2_10GEC1_1   0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_2   0x40000000
+#else
 #define FSL_CORENET_DEVDISR2_10GEC1_1  0x00800000
 #define FSL_CORENET_DEVDISR2_10GEC1_2  0x00400000
 #define FSL_CORENET_DEVDISR2_10GEC1_3  0x80000000
 #define FSL_CORENET_DEVDISR2_10GEC1_4  0x40000000
+#endif
 #define FSL_CORENET_DEVDISR2_DTSEC2_1  0x00080000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00040000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00020000
@@ -1787,6 +1793,21 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define PXCKEN_MASK    0x80000000
 #define PXCK_MASK      0x00FF0000
 #define PXCK_BITS_START        16
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
+       defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff800000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  23
+#define FSL_CORENET_RCWSR6_BOOT_LOC            0x0f800000
+#define FSL_CORENET_RCWSR13_EC1                        0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_RGMII          0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO           0x10000000
+#define FSL_CORENET_RCWSR13_EC2                        0x0c000000
+#define FSL_CORENET_RCWSR13_EC2_RGMII          0x08000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET    0x28
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET    0xd00
+#define PXCKEN_MASK                            0x80000000
+#define PXCK_MASK                              0x00FF0000
+#define PXCK_BITS_START                                16
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
@@ -2803,21 +2824,6 @@ struct ccsr_pman {
        u8      res_f4[0xf0c];
 };
 #endif
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
-struct ccsr_sfp_regs {
-       u32 ospr;               /* 0x200 */
-       u32 reserved0[14];
-       u32 srk_hash[8];        /* 0x23c Super Root Key Hash */
-       u32 oem_uid;            /* 0x9c OEM Unique ID */
-       u8 reserved2[0x04];
-       u32 ovpr;                       /* 0xA4  Intent To Secure */
-       u8 reserved4[0x08];
-       u32 fsl_uid;            /* 0xB0  FSL Unique ID */
-       u8 reserved5[0x04];
-       u32 fsl_spfr0;          /* Scratch Pad Fuse Register 0 */
-       u32 fsl_spfr1;          /* Scratch Pad Fuse Register 1 */
-};
-#endif
 
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET      0x0000
@@ -2877,6 +2883,7 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x300000
 #define CONFIG_SYS_FSL_JR0_OFFSET              0x301000
+#define CONFIG_SYS_SEC_MON_OFFSET              0x314000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET      0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET             0x31a000
@@ -2944,7 +2951,7 @@ struct ccsr_sfp_regs {
 #endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
-#define CONFIG_SYS_SNVS_OFFSET                 0xE6000
+#define CONFIG_SYS_SEC_MON_OFFSET              0xE6000
 #define CONFIG_SYS_SFP_OFFSET                  0xE7000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET          0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
@@ -2971,6 +2978,8 @@ struct ccsr_sfp_regs {
        (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR        \
        (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
+       (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \
@@ -3072,6 +3081,9 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_SFP_ADDR  \
        (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
 
+#define CONFIG_SYS_SEC_MON_ADDR  \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+
 #define TSEC_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)