powerpc/mp: add support for discontiguous cores

[u-boot] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index d6ac61afaf53997ad6c440df5a1552cc78c03a5b..6aaade076ee4a1e37cecf9d25d732431a221c219 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1759,7 +1759,8 @@ typedef struct ccsr_gur {
        u32     cgencrl;        /* Core general control */
        u8      res31[184];
        u32     sriopstecr;     /* SRIO prescaler timer enable control */
-       u8      res32[1788];
+       u32     dcsrcr;         /* DCSR Control register */
+       u8      res32[1784];
        u32     pmuxcr;         /* Pin multiplexing control */
        u8      res33[60];
        u32     iovselsr;       /* I/O voltage selection status */
@@ -1772,6 +1773,10 @@ typedef struct ccsr_gur {
        u8      res37[380];
 } ccsr_gur_t;
 
+#define FSL_CORENET_DCSR_SZ_MASK       0x00000003
+#define FSL_CORENET_DCSR_SZ_4M         0x0
+#define FSL_CORENET_DCSR_SZ_1G         0x3
+
 /*
  * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
  * everything after has RMan thus msg unit LIODN is used for maintenance
@@ -2017,7 +2022,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE                0x00001000
 #endif
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
-#define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f1000
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f8000
 #define MPC85xx_PMUXCR2_USB            0x00150000
 #endif
        u8      res6[8];
@@ -2101,6 +2106,7 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_100       0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125       0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25    0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150       0x30000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK     0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5                0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25     0x00010000
@@ -2137,6 +2143,9 @@ typedef struct serdes_corenet {
 #define SRDS_TECR0_TEQ_TYPE_2LVL       0x10000000
                u32     res3;
                u32     ttlcr0; /* Transition Tracking Loop Ctrl 0 */
+#define SRDS_TTLCR0_FLT_SEL_MASK       0x3f000000
+#define SRDS_TTLCR0_FLT_SEL_750PPM     0x03000000
+#define SRDS_TTLCR0_PM_DIS             0x00004000
                u32     res4[7];
        } lane[24];
        u32 res6[384];
@@ -2285,6 +2294,13 @@ typedef struct ccsr_pme {
        u8      res4[0x400];
 } ccsr_pme_t;
 
+typedef struct ccsr_usb_phy {
+       u8      res0[0x18];
+       u32     usb_enable_override;
+       u8      res[0xe4];
+} ccsr_usb_phy_t;
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET      0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET          0x8000
@@ -2307,6 +2323,8 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x211000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET          CONFIG_SYS_MPC85xx_USB1_OFFSET
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET                0x220000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x300000
@@ -2429,6 +2447,10 @@ typedef struct ccsr_pme {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_FM1_ADDR \