powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs

[u-boot] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index e2f3ae9ab50dbf4e38d942de8c0925d9e2f87c0f..6c11178f0f46a3787198850113da65f4748c280d 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
        u32     cfg_addr;       /* PCIX Configuration Addr */
        u32     cfg_data;       /* PCIX Configuration Data */
        u32     int_ack;        /* PCIX IRQ Acknowledge */
-       u8      res1[3060];
+       u8      res000c[52];
+       u32     liodn_base;     /* PCIX LIODN base register */
+       u8      res0044[3004];
        u32     potar0;         /* PCIX Outbound Transaction Addr 0 */
        u32     potear0;        /* PCIX Outbound Translation Extended Addr 0 */
        u32     powbar0;        /* PCIX Outbound Window Base Addr 0 */
@@ -2621,6 +2623,7 @@ struct ccsr_rman {
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET      0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET          0x8000
 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET         0x9000
+#define CONFIG_SYS_MPC85xx_DDR3_OFFSET         0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET      0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET     0xE2000
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET   0xEA000
@@ -2631,6 +2634,7 @@ struct ccsr_rman {
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET         0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x114000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET          0x124000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0x130000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET     0x1e0000
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET                0x200000
@@ -2739,6 +2743,8 @@ struct ccsr_rman {
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
 #define CONFIG_SYS_MPC85xx_DDR2_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR3_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
 #define CONFIG_SYS_IFC_ADDR \