* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_85xx__
#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#elif defined(CONFIG_PPC_T1040)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
#define FSL_CORENET_DCSR_SZ_4M 0x0
#define rmuliodnr rio1maintliodnr
typedef struct ccsr_clk {
- u32 clkc0csr; /* 0x000 Core 0 Clock control/status */
- u8 res1[0x1c];
- u32 clkc1csr; /* 0x020 Core 1 Clock control/status */
- u8 res2[0x1c];
- u32 clkc2csr; /* 0x040 Core 2 Clock control/status */
- u8 res3[0x1c];
- u32 clkc3csr; /* 0x060 Core 3 Clock control/status */
- u8 res4[0x1c];
- u32 clkc4csr; /* 0x080 Core 4 Clock control/status */
- u8 res5[0x1c];
- u32 clkc5csr; /* 0x0a0 Core 5 Clock control/status */
- u8 res6[0x1c];
- u32 clkc6csr; /* 0x0c0 Core 6 Clock control/status */
- u8 res7[0x1c];
- u32 clkc7csr; /* 0x0e0 Core 7 Clock control/status */
- u8 res8[0x71c];
+ struct {
+ u32 clkcncsr; /* core cluster n clock control status */
+ u8 res_004[0x0c];
+ u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
+ u8 res_014[0x0c];
+ } clkcsr[8];
+ u8 res_100[0x700]; /* 0x100 */
u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */
u8 res10[0x1c];
u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */
u32 porbmsr; /* POR boot mode status */
#define MPC85xx_PORBMSR_HA 0x00070000
#define MPC85xx_PORBMSR_HA_SHIFT 16
-#define MPC85XX_PORBMSR_ROMLOC_SHIFT 24
+#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
#define PORBMSR_ROMLOC_SPI 0x6
#define PORBMSR_ROMLOC_SDHC 0x7
#define PORBMSR_ROMLOC_NAND_2K 0x9