Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0264523d6402779e094ed5fee993f9fddcc95be0..ace1d120c647c313f237fcb1763b9da6873452b7 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1626,10 +1626,15 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC1_6  0x04000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_9  0x00800000
 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
+#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define FSL_CORENET_DEVDISR2_10GEC1_1   0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_2   0x40000000
+#else
 #define FSL_CORENET_DEVDISR2_10GEC1_1  0x00800000
 #define FSL_CORENET_DEVDISR2_10GEC1_2  0x00400000
 #define FSL_CORENET_DEVDISR2_10GEC1_3  0x80000000
 #define FSL_CORENET_DEVDISR2_10GEC1_4  0x40000000
+#endif
 #define FSL_CORENET_DEVDISR2_DTSEC2_1  0x00080000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00040000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00020000
@@ -1787,6 +1792,21 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define PXCKEN_MASK    0x80000000
 #define PXCK_MASK      0x00FF0000
 #define PXCK_BITS_START        16
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
+       defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff800000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  23
+#define FSL_CORENET_RCWSR6_BOOT_LOC            0x0f800000
+#define FSL_CORENET_RCWSR13_EC1                        0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_RGMII          0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO           0x10000000
+#define FSL_CORENET_RCWSR13_EC2                        0x0c000000
+#define FSL_CORENET_RCWSR13_EC2_RGMII          0x08000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET    0x28
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET    0xd00
+#define PXCKEN_MASK                            0x80000000
+#define PXCK_MASK                              0x00FF0000
+#define PXCK_BITS_START                                16
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
@@ -2971,6 +2991,8 @@ struct ccsr_sfp_regs {
        (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR        \
        (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
+       (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \